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AD9574BCPZ

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipad9574bcpzfactory-2.0.0extractor-text

Verified AD9574BCPZ

by Ray · last 30 Oct 2026 · 1 record · files match
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30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9574BCPZ · LFCSP-48(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 35-page datasheet
  • ✓distributor: lcsc C653596, digikey 505-AD9574BCPZ-ND, mouser 584-AD9574BCPZ
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-uqalk74c/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.35)
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
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Symbol & Footprint

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Contents

README

markdown

AD9574BCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-48(7x7)

AD9574BCPZ from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF0_P input Reference Clock Input 0, Positive, configurable via PPR0 (Pin 47).
2 REF0_N input Reference Clock Input 0, Negative, configurable via PPR0 (Pin 47).
3 VDD_REF0 power_in 3.3 V input supply for Reference Clock Input 0 (REF0_x), supplying the single-ended input receiver and internal LDO regulator for the differential receiver.
4 VDD_REF1 power_in 3.3 V input supply for Reference Clock Input 1 (REF1_x), supplying the single-ended input receiver and internal LDO regulator for the differential receiver.
5 REF1_N input Reference Clock Input 1, Negative, configurable via PPR0 (Pin 47).
6 REF1_P input Reference Clock Input 1, Positive, configurable via PPR0 (Pin 47).
7 PPR2 input Pin Program Reader 2; connect a resistor to this pin to configure the OUT0 and OUT1 channels.
8 VDD_OUT01 power_in 3.3 V input for the CMOS drivers of OUT0_x and OUT1_x and source for an internal 1.8 V LDO regulator for their differential drivers.
9 OUT0_N output Clock Output 0, Negative, configurable via PPR2 (Pin 7).
10 OUT0_P output Clock Output 0, Positive, configurable via PPR2 (Pin 7).
11 OUT1_P output Clock Output 1, Positive, configurable via PPR2 (Pin 7).
12 OUT1_N output Clock Output 1, Negative, configurable via PPR2 (Pin 7).
13 VDD_PLL power_in 3.3 V input to the internal LDO regulator for the PLL.
14 LD output 3.3 V CMOS PLL lock detector status; Logic 0 = unlocked, Logic 1 = locked.
15 LF passive Analog loop filter; connect a capacitor or series RC network from this pin to LDO_BYP (Pin 16).
16 LDO_BYP passive Analog LDO bypass; connect a 470 nF capacitor from this pin to GND.
17 VDD_VCO power_in 3.3 V input to the internal LDO regulator for the VCO.
18 VDD_RFDIV power_in 3.3 V input to the internal LDO regulator for the VCO RF dividers.
19 PPR6 input Pin Program Reader 6; connect a resistor to this pin to configure the MCLK_x input.
20 RESET input 3.3 V CMOS reset; Logic 0 (GND) initializes the device to its default state, with an internal 30 kΩ pull-up resistor.
21 OUT6_N output Clock Output 6, Negative, configurable via PPR4 (Pin 26).
22 OUT6_P output Clock Output 6, Positive, configurable via PPR4 (Pin 26).
23 VDD_OUT6 power_in 3.3 V input for the CMOS drivers of OUT6_x and source for an internal 1.8 V LDO regulator for the 1.8 V CMOS and differential drivers of OUT6_x.
24 PPR5 input Pin Program Reader 5; connect a resistor to this pin to configure the reference clock frequency error threshold.
25 REFMON input Reference frequency monitor enable/disable; do not float or toggle during operation, connect to a static Logic 0 or Logic 1.
26 PPR4 input Pin Program Reader 4; connect a resistor to this pin to configure the OUT6 channel.
27 PPR3 input Pin Program Reader 3; connect a resistor to this pin to configure the OUT4 and OUT5 channels.
28 OUT4_N output Clock Output 4, Negative, configurable via PPR3 (Pin 27).
29 OUT4_P output Clock Output 4, Positive, configurable via PPR3 (Pin 27).
30 VDD_OUT4 power_in 3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT4_x.
31 VDD_OUT5 power_in 3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT5_x.
32 OUT5_P output Clock Output 5, Positive, configurable via PPR3 (Pin 27).
33 OUT5_N output Clock Output 5, Negative, configurable via PPR3 (Pin 27).
34 REF_FLO output 3.3 V CMOS low reference frequency status; Logic 1 indicates reference below the lower threshold, open-drain with internal 30 kΩ pull-down.
35 REF_FHI output 3.3 V CMOS high reference frequency status; Logic 1 indicates reference above the upper threshold, open-drain with internal 30 kΩ pull-down.
36 VDD_OUT23 power_in 3.3 V input for an internal 1.8 V LDO regulator for the differential drivers of OUT2_x and OUT3_x.
37 OUT2_N output Clock Output 2, Negative (HSTL).
38 OUT2_P output Clock Output 2, Positive (HSTL).
39 OUT3_P output Clock Output 3, Positive (HSTL).
40 OUT3_N output Clock Output 3, Negative (HSTL).
41 PPR1 input Pin Program Reader 1; connect a resistor to this pin to select a predefined frequency translation configuration.
42 VDD_MCLK power_in 3.3 V input for Reference Monitor Clock (MCLK_x), supplying the single-ended input receiver and internal LDO regulator for the differential receiver.
43 REF_SW output 3.3 V CMOS reference switchover status indicator showing when the device is switching references.
44 REF_ACT output 3.3 V CMOS reference active status indicator showing whether REF0 or REF1 is the active reference.
45 MCLK_P input Reference monitor clock normal input, configurable via PPR6.
46 MCLK_N input Reference monitor clock complementary input, configurable via PPR6.
47 PPR0 input Pin Program Reader 0; connect a resistor to this pin to configure the reference clock inputs.
48 REF_SEL input 3.3 V CMOS reference clock select (Logic 0 = REF0, Logic 1 = REF1), with internal 30 kΩ pull-down.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category RTC/Clock Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage VS 2.97 3.3 3.63 V 10
Power Dissipation, Typical Configuration 466 569 654 mW PPR0 State 0, PPR1 State 0, PPR2 State 7, PPR3 State 0, PPR4 State 5, PPR5 State 0, PPR6 State 0, REFMON: GND 10
Power Dissipation, All Blocks Running 579 698 803 mW PPR0 State 4, PPR1 State 0, PPR2 State 2, PPR3 State 2, PPR4 State 1, PPR5 State 6, PPR6 State 4, REFMON: VDD 10
Power Dissipation, Minimal Power Configuration 346 422 486 mW PPR0 State 0, PPR1 State 4, PPR2 State 4, PPR3 State 7, PPR4 State 0, PPR5 State 0, PPR6 State 1, REFMON: GND 11
Supply Current, Typical Configuration ISUPPLY 157 172 180 mA Total supply current for VDD_x pins in aggregate; typical configuration settings 11
Supply Current, All Blocks Running ISUPPLY 195 212 221 mA Total supply current for VDD_x pins in aggregate; all blocks running configuration settings 11
Supply Current, Minimal Power ISUPPLY 117 128 134 mA Total supply current for VDD_x pins in aggregate; minimal power configuration settings 11
Incremental Power, Input Reference Single-Ended 0.23 0.3 0.36 mW Applies to one reference clock input 11
Incremental Power, Input Reference Differential 20.5 25.1 30 mW Applies to one reference clock input 11
Incremental Power, LVDS driver (312.5 MHz) 18.1 22.5 27.2 mW Output driver on/off 11
Incremental Power, HSTL driver (156.25 MHz) 30.6 36.6 42.5 mW Output driver on/off 11
Incremental Power, 1.8 V CMOS driver (66 MHz) 13.7 16.2 19.2 mW A single 1.8 V CMOS output with an 10 pF load 11
Incremental Power, 3.3 V CMOS driver (25 MHz) 9.5 12.2 15.2 mW A single 3.3 V CMOS output with an 10 pF load 11
Incremental Power, OUT0 ×2 3.1 4 5.4 mW OUT0 ×2 On/Off 11
HSTL Differential Output Voltage Swing 745 955 1235 mV 100 Ω termination (differential); output driver static 6
HSTL Common-Mode Output Voltage 745 950 1010 mV 100 Ω termination (differential); output driver static 6
HCSL Differential Output Voltage Swing 570 700 830 mV 50 Ω from each output pin to GND; output driver static 6
HCSL Common-Mode Output Voltage 295 360 430 mV 50 Ω from each output pin to GND; output driver static 6
LVDS Differential Output Voltage VOD 247 350 454 mV 100 Ω termination (differential); output driver static 6
LVDS Output Offset Voltage VOS 1.125 1.25 1.375 V 100 Ω termination (differential) 6
LVDS Short-Circuit Current ISA, ISB 14 24 mA Output shorted to GND 6
1.8 V CMOS Output High Voltage VOH 1.7 V ILOAD = 1 mA 6
1.8 V CMOS Output Low Voltage VOL 0.1 V ILOAD = 1 mA 6
3.3 V CMOS Output Low Voltage VOL 0.5 V ILOAD = 10 mA 6
HSTL OUT0/OUT1 Output Rise Time tRL 161 195 232 ps Measured differentially 6
HSTL OUT0/OUT1 Output Fall Time tFL 164 193 226 ps Measured differentially 6
HSTL OUT2-OUT5 Output Rise Time tRP 114 144 175 ps Measured differentially 6
HSTL OUT2-OUT5 Output Fall Time tFP 111 143 177 ps Measured differentially 6
HCSL Output Rise Time tRL 195 206 221 ps Measured differentially 6
HCSL Output Fall Time tFL 188 211 238 ps Measured differentially 6
LVDS OUT4/OUT5 Output Rise Time tRL 151 193 238 ps Measured differentially 7
LVDS OUT4/OUT5 Output Fall Time tFL 152 195 242 ps Measured differentially 7
LVDS OUT6 Output Rise Time tRL 221 242 273 ps Measured differentially 7
LVDS OUT6 Output Fall Time tFL 224 241 270 ps Measured differentially 7
Reference Input Differential Common-Mode Voltage Tolerance 0.65 1.8 V Acceptable common-mode range for a 200 mV p-p dc-coupled input signal 8
Monitor Clock Differential Common-Mode Voltage Tolerance 0.6 1.5 V Acceptable common-mode range for a 200 mV p-p dc-coupled input signal 7
REF_SEL Logic 1 Voltage VIH 2 V Internal 30 kΩ pull-down resistor 9
REF_SEL Logic 0 Voltage VIL 0.8 V Internal 30 kΩ pull-down resistor 9
RESET Logic 1 Voltage VIH 2 V Internal 30 kΩ pull-up resistor 9
RESET Logic 0 Voltage VIL 0.8 V Internal 30 kΩ pull-up resistor 9
Reference Switchover Frequency Disturbance 250 500 ppm pk Applies only to PLL outputs; 1 ppm frequency offset between the REF0 and REF1 channels 9
Absolute Max VDD_x to GND VDD_x -0.3 3.6 V 13
Absolute Max Junction Temperature TJ 150 °C 13
Storage Temperature Range -65 150 °C 13
Operating Temperature Range TA -40 85 °C 1
Junction to ambient thermal resistance θJA 32.6 °C/W 0.0 m/sec airflow, JEDEC JESD51-2 (still air) 34
Junction to board thermal resistance θJB 18.7 °C/W 0.0 m/sec airflow, JEDEC JESD51-8 (still air) 34
Junction to case thermal resistance θJC 3.5 °C/W per MIL-Standard 883, Method 1012.1 34
Junction to top characterization parameter ΨJT 0.3 °C/W 0 m/sec airflow, JEDEC JESD51-2 (still air) 34
HSTL Duty Cycle OUT0/OUT1 45 55 % Assumes 50% reference input duty cycle; does not apply to OUT0_x for 38.88 MHz and 50 MHz operation 6
HSTL Duty Cycle OUT2-OUT5 45 55 % 6
1.8 V CMOS Output Rise Time tRC 1.2 1.7 ns CLOAD = 10 pF 7
1.8 V CMOS Output Fall Time tFC 1.2 1.8 ns CLOAD = 10 pF 7
3.3 V CMOS Output Rise Time tRC 0.5 1 ns CLOAD = 10 pF 7
3.3 V CMOS Output Fall Time tFC 0.6 1.1 ns CLOAD = 10 pF 7

CAD (KiCad official)

  • Symbol: AD9574BCPZ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9574bcpz-etched.step / ad9574bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9574bcpz.step / ad9574bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (35 pp, sha256 d2a8390399782645, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF