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ADUM2401ARWZ-RL
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Analog Devices Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownADUM2401ARWZ-RL
Analog Devices · Digital Isolators · SOIC-16
ADUM2401ARWZ-RL from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, specified at 2.7 V to 5.5 V. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1; pin 2 is internally connected to pin 8, and connecting both to GND1 is recommended. |
| 3 | VIA | input | Logic input A on side 1 of the isolation barrier. |
| 4 | VIB | input | Logic input B on side 1 of the isolation barrier. |
| 5 | VIC | input | Logic input C on side 1 of the isolation barrier. |
| 6 | VOD | output | Logic output D; it is enabled when VE1 is high or disconnected and disabled when VE1 is low. |
| 7 | VE1 | input | Output enable 1, an active-high logic input for VOD; connecting it to an external logic high or low is recommended in noisy environments. |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1; internally connected to pin 2, and connecting both to GND1 is recommended. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2; internally connected to pin 15, and connecting both to GND2 is recommended. |
| 10 | VE2 | input | Output enable 2, an active-high logic input for VOA, VOB, and VOC; those outputs are enabled when VE2 is high or disconnected and disabled when VE2 is low, and connecting VE2 to an external logic high or low is recommended in noisy environments. |
| 11 | VID | input | Logic input D on side 2 of the isolation barrier. |
| 12 | VOC | output | Logic output C on side 2 of the isolation barrier. |
| 13 | VOB | output | Logic output B on side 2 of the isolation barrier. |
| 14 | VOA | output | Logic output A on side 2 of the isolation barrier. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2; internally connected to pin 9, and connecting both to GND2 is recommended. |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, specified at 2.7 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature (TA) | TA | -40 | 105 | °C | 11 | ||
| Supply Voltages (VDD1, VDD2) | VDD1, VDD2 | 2.7 | 5.5 | V | 11 | ||
| Input Signal Rise and Fall Times | 1 | ms | 11 | ||||
| Storage Temperature Range | TST | -65 | 150 | °C | 12 | ||
| Supply Voltage Range | VDD1, VDD2 | -0.5 | 7 | V | 12 | ||
| Input Voltage Range | VIA, VIB, VIC, VID, VE1, VE2 | -0.5 | V | 12 | |||
| Output Voltage Range | VOA, VOB, VOC, VOD | -0.5 | V | 12 | |||
| Average Output Current Per Pin, Side 1 | IO1 | -18 | 18 | mA | 12 | ||
| Average Output Current Per Pin, Side 2 | IO2 | -22 | 22 | mA | 12 | ||
| Common-Mode Transients | -100 | 100 | kV/µs | Refers to common-mode transients across the insulation barrier | 12 | ||
| Minimum External Air Gap (RW-16) | L(I01) | 8 | mm | Distance from input terminals to output terminals, shortest distance through air along PCB mounting plane | 10 | ||
| Minimum External Tracking (Creepage) RW-16 Package | L(I02) | 7.7 | mm | Measured from input terminals to output terminals, shortest distance path along body | 10 | ||
| Minimum Internal Gap (Internal Clearance) | 0.017 | mm | Insulation distance through insulation | 10 | |||
| Input Supply Current per Channel, Quiescent (5 V operation) | IDDI (Q) | 0.5 | 0.53 | mA | 3 | ||
| Output Supply Current per Channel, Quiescent (5 V operation) | IDDO (Q) | 0.19 | 0.21 | mA | 3 | ||
| ADuM2401 VDD1 Supply Current, Four Channels, Quiescent (5 V operation) | IDD1 (Q) | 1.8 | 2.4 | mA | DC to 1 MHz logic signal frequency | 3 | |
| ADuM2401 VDD2 Supply Current, Four Channels, Quiescent (5 V operation) | IDD2 (Q) | 1.2 | 1.8 | mA | DC to 1 MHz logic signal frequency | 3 | |
| Input Currents (5 V operation) | IIA, IIB, IIC, IID, IE1, IE2 | -10 | 0.01 | 10 | µA | 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 | 3 |
| Logic High Input Threshold (5 V operation) | VIH, VEH | 2 | V | 3 | |||
| Logic Low Input Threshold (5 V operation) | VIL, VEL | 0.8 | V | 3 | |||
| Logic Low Output Voltage (5 V operation) | VOAL, VOBL, VOCL, VODL | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 3 | |
| Logic Low Output Voltage (5 V operation) | VOAL, VOBL, VOCL, VODL | 0.04 | 0.1 | V | IOx = 400 µA, VIx = VIxL | 3 | |
| Logic Low Output Voltage (5 V operation) | VOAL, VOBL, VOCL, VODL | 0.2 | 0.4 | V | IOx = 4 mA, VIx = VIxL | 3 | |
| Minimum Pulse Width (5 V operation) | PW | 1000 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Maximum Data Rate (5 V operation) | 1 | Mbps | CL = 15 pF, CMOS signal levels | 3 | |||
| Propagation Delay (5 V operation) | tPHL, tPLH | 50 | 65 | 100 | ns | CL = 15 pF, CMOS signal levels | 3 |
| Pulse Width Distortion, /tPLH − tPHL/ (5 V operation) | PWD | 40 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Propagation Delay Skew (5 V operation) | tPSK | 50 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Channel-to-Channel Matching (5 V operation) | tPSKCD/tPSKOD | 50 | ns | CL = 15 pF, CMOS signal levels | 3 | ||
| Output Disable Propagation Delay (High/Low to High Impedance) (5 V operation) | tPHZ, tPLH | 6 | 8 | ns | CL = 15 pF, CMOS signal levels | 4 | |
| Output Enable Propagation Delay (High Impedance to High/Low) (5 V operation) | tPZH, tPZL | 6 | 8 | ns | CL = 15 pF, CMOS signal levels | 4 | |
| Common-Mode Transient Immunity at Logic High Output (5 V operation) | /CMH/ | 25 | 35 | kV/µs | VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| Common-Mode Transient Immunity at Logic Low Output (5 V operation) | /CML/ | 25 | 35 | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 4 | |
| Input Supply Current per Channel, Quiescent (3 V operation) | IDDI (Q) | 0.26 | 0.31 | mA | 5 | ||
| Output Supply Current per Channel, Quiescent (3 V operation) | IDDO (Q) | 0.11 | 0.14 | mA | 5 | ||
| ADuM2401 VDD1 Supply Current, Four Channels, Quiescent (3 V operation) | IDD1 (Q) | 1 | 1.6 | mA | DC to 1 MHz logic signal frequency | 5 | |
| ADuM2401 VDD2 Supply Current, Four Channels, Quiescent (3 V operation) | IDD2 (Q) | 0.7 | 1.2 | mA | DC to 1 MHz logic signal frequency | 5 | |
| Input Currents (3 V operation) | IIA, IIB, IIC, IID, IE1, IE2 | -10 | 0.01 | 10 | µA | 0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2 | 5 |
| Logic High Input Threshold (3 V operation) | VIH, VEH | 1.6 | V | 5 | |||
| Logic Low Input Threshold (3 V operation) | VIL, VEL | 0.4 | V | 5 | |||
| Logic Low Output Voltage (3 V operation) | VOAL, VOBL, VOCL, VODL | 0 | 0.1 | V | IOx = 20 µA, VIx = VIxL | 5 | |
| Logic Low Output Voltage (3 V operation) | VOAL, VOBL, VOCL, VODL | 0.04 | 0.1 | V | IOx = 400 µA, VIx = VIxL | 5 | |
| Logic Low Output Voltage (3 V operation) | VOAL, VOBL, VOCL, VODL | 0.2 | 0.4 | V | IOx = 4 mA, VIx = VIxL | 5 | |
| Minimum Pulse Width (3 V operation) | PW | 1000 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Maximum Data Rate (3 V operation) | 1 | Mbps | CL = 15 pF, CMOS signal levels | 5 | |||
| Propagation Delay (3 V operation) | tPHL, tPLH | 50 | 75 | 100 | ns | CL = 15 pF, CMOS signal levels | 5 |
| Pulse Width Distortion, /tPLH − tPHL/ (3 V operation) | PWD | 40 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Propagation Delay Skew (3 V operation) | tPSK | 50 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Channel-to-Channel Matching (3 V operation) | tPSKCD/tPSKOD | 50 | ns | CL = 15 pF, CMOS signal levels | 5 | ||
| Output Disable Propagation Delay (High/Low to High Impedance) (3 V operation) | tPHZ, tPLH | 6 | 8 | ns | CL = 15 pF, CMOS signal levels | 6 | |
| Output Enable Propagation Delay (High Impedance to High/Low) (3 V operation) | tPZH, tPZL | 6 | 8 | ns | CL = 15 pF, CMOS signal levels | 6 | |
| Common-Mode Transient Immunity at Logic High Output (3 V operation) | /CMH/ | 25 | 35 | kV/µs | VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V | 6 | |
| Common-Mode Transient Immunity at Logic Low Output (3 V operation) | /CML/ | 25 | 35 | kV/µs | VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V | 6 | |
| Logic High Output Voltage (5 V operation, minimum expressed as (VDD1 or VDD2) − 0.1 V) | VOAH, VOBH, VOCH, VODH | 5 | V | IOx = −20 µA, VIx = VIxH | 3 | ||
| Logic High Output Voltage (5 V operation, minimum expressed as (VDD1 or VDD2) − 0.4 V) | VOAH, VOBH, VOCH, VODH | 4.8 | V | IOx = −4 mA, VIx = VIxH | 3 | ||
| Logic High Output Voltage (3 V operation, minimum expressed as (VDD1 or VDD2) − 0.1 V) | VOAH, VOBH, VOCH, VODH | 3 | V | IOx = −20 µA, VIx = VIxH | 5 | ||
| Logic High Output Voltage (3 V operation, minimum expressed as (VDD1 or VDD2) − 0.4 V) | VOAH, VOBH, VOCH, VODH | 2.8 | V | IOx = −4 mA, VIx = VIxH | 5 | ||
| IC Junction-to-Case Thermal Resistance, Side 1 | θJCI | 33 | °C/W | Thermocouple located at center of package underside | 10 | ||
| IC Junction-to-Case Thermal Resistance, Side 2 | θJCO | 28 | °C/W | Thermocouple located at center of package underside | 10 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | detection limit = 10 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM2400/ADuM2401/ADuM2402 is proof tested by applying an insulation test voltage ≥1590 V peak for 1 sec (partial discharge det | 10 |
CAD (KiCad official)
- Symbol:
ADUM2401ARWZ-RL - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
adum2401arwz-rl-etched.step/adum2401arwz-rl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adum2401arwz-rl.step/adum2401arwz-rl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
0b0077603f231152, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).