component

CD4002NS14ARDQ

Public Made by Adom

by adom

GR Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4002ns14ardqfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CD4002NS14ARDQ

GR · Logic Gates · SOP-14

CD4002NS14ARDQ from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Data output of NOR gate 1; per the truth table, Y is high only when all of its inputs (1A to 1D) are low.
2 1A input Data input A of NOR gate 1.
3 1B input Data input B of NOR gate 1.
4 1C input Data input C of NOR gate 1.
5 1D input Data input D of NOR gate 1.
6 NC unconnected Not connected; the datasheet assigns no function to this pin.
7 VSS power_in Ground reference for all voltages in the datasheet (VSS = 0 V).
8 NC unconnected Not connected; the datasheet assigns no function to this pin.
9 2A input Data input A of NOR gate 2.
10 2B input Data input B of NOR gate 2.
11 2C input Data input C of NOR gate 2.
12 2D input Data input D of NOR gate 2.
13 2Y output Data output of NOR gate 2; per the truth table, Y is high only when all of its inputs (2A to 2D) are low.
14 VDD power_in Supply voltage; the datasheet's absolute maximum DC supply range is -0.5 V to 20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Range (Voltage Referenced to VSS Terminals) VDD -0.5 20 V Voltage referenced to VSS terminals 3
Input Voltage Range, All Inputs VI 0.5 V 3
Power Dissipation PD 500 mW 3
Junction Temperature TJ 125 ℃ 3
Operating Temperature TOP -40 85 ℃ 3
Supply Current IDD 0 1 uA VIN=0, VDD=5, Ta=25℃ 3
Low Level Output Current IOL 1.5 3 mA VO=0.4, VIN=0 or 5, VDD=5, Ta=25℃ 3
Low Level Output Current IOL 4 8 mA VO=0.5, VIN=0 or 10, VDD=10, Ta=25℃ 3
Low Level Output Current IOL 15 30 mA VO=1.5, VIN=0 or 15, VDD=15, Ta=25℃ 3
High Level Output Current IOH -0.5 -2 mA VO=4.6, VIN=0 or 5, VDD=5, Ta=25℃ 3
High Level Output Current IOH -4 -8 mA VO=2.5, VIN=0 or 5, VDD=5, Ta=25℃ 3
High Level Output Current IOH -2 -4 mA VO=9.5, VIN=0 or 10, VDD=10, Ta=25℃ 3
High Level Output Current IOH -7 -14 mA VO=13.5, VIN=0 or 15, VDD=15, Ta=25℃ 3
Low Level Output Voltage VOL 0 0.05 V VIN=0 or 5, VDD=5, Ta=25℃ 3
High Level Output Voltage VOH 4.95 5 V VIN=0 or 5, VDD=5, Ta=25℃ 3
High Level Output Voltage VOH 9.95 10 V VIN=0 or 10, VDD=10, Ta=25℃ 3
High Level Output Voltage VOH 14.95 15 V VIN=0 or 15, VDD=15, Ta=25℃ 3
Low Level Input Voltage VIL 1.5 V VO=0.5 or 4.5, VDD=5, Ta=25℃ 3
Low Level Input Voltage VIL 3 V VO=1 or 9, VDD=10, Ta=25℃ 3
Low Level Input Voltage VIL 4 V VO=1.5 or 13.5, VDD=15, Ta=25℃ 3
High Level Input Voltage VIH 3.5 V VO=0.5 or 4.5, VDD=5, Ta=25℃ 3
High Level Input Voltage VIH 7 V VO=1 or 9, VDD=10, Ta=25℃ 3
High Level Input Voltage VIH 11 V VO=1.5 or 13.5, VDD=15, Ta=25℃ 3
Input Leakage Current IIN -1 0 1 uA VIN=0 or 18, VDD=18, Ta=25℃ 3

CAD (KiCad official)

  • Symbol: CD4002NS14ARDQ
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4002ns14ardq-etched.step / cd4002ns14ardq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4002ns14ardq.step / cd4002ns14ardq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (7 pp, sha256 64b0f1716714382d, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF