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SN74F38DR

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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74F38DR

Texas Instruments · Logic Gates · SOIC-14

SN74F38DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input A of NAND buffer gate 1; the gate performs Y = A • B (positive logic) and the input current range is −30 mA to 5 mA.
2 1B input Data input B of NAND buffer gate 1; the gate performs Y = A • B (positive logic) and the input current range is −30 mA to 5 mA.
3 1Y output Open-collector output of gate 1 that requires an external pullup resistor to operate correctly and may be wired-OR connected with other open-collector outputs.
4 2A input Data input A of NAND buffer gate 2; the gate performs Y = A • B (positive logic) and the input current range is −30 mA to 5 mA.
5 2B input Data input B of NAND buffer gate 2; the gate performs Y = A • B (positive logic) and the input current range is −30 mA to 5 mA.
6 2Y output Open-collector output of gate 2 that requires an external pullup resistor to operate correctly and may be wired-OR connected with other open-collector outputs.
7 GND power_in Ground reference for the device.
8 3Y output Open-collector output of gate 3 that requires an external pullup resistor to operate correctly and may be wired-OR connected with other open-collector outputs.
9 3A input Data input A of NAND buffer gate 3; the gate performs Y = A • B (positive logic) and the input current range is −30 mA to 5 mA.
10 3B input Data input B of NAND buffer gate 3; the gate performs Y = A • B (positive logic) and the input current range is −30 mA to 5 mA.
11 4Y output Open-collector output of gate 4 that requires an external pullup resistor to operate correctly and may be wired-OR connected with other open-collector outputs.
12 4A input Data input A of NAND buffer gate 4; the gate performs Y = A • B (positive logic) and the input current range is −30 mA to 5 mA.
13 4B input Data input B of NAND buffer gate 4; the gate performs Y = A • B (positive logic) and the input current range is −30 mA to 5 mA.
14 VCC power_in Supply voltage, recommended 4.5 V to 5.5 V (nominal 5 V) with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 2
Input voltage VI -0.5 7 V See Note 1: may be exceeded provided input current ratings are observed 2
Input current range -30 5 mA 2
Voltage range applied to any output in the high state -0.5 V Maximum printed as VCC; numeric value not given 2
Current into any output in the low state 128 mA 2
Operating free-air temperature range (SN74F38) TA 0 70 °C 2
Storage temperature range Tstg -65 150 °C 2
Supply voltage VCC 4.5 5 5.5 V 2
High-level input voltage VIH 2 V 2
Low-level input voltage VIL 0.8 V 2
Input clamp current IIK -18 mA 2
High-level output voltage VOH 4.5 V 2
Low-level output current IOL 64 mA 2
Operating free-air temperature (SN74F38) TA 0 70 °C 2
Input clamp voltage VIK -1.2 V VCC = 4.5 V, II = −18 mA 2
Low-level output voltage VOL 0.3 0.5 V VCC = 4.5 V, IOL = 48 mA 2
Input current at maximum input voltage II 0.1 mA VCC = 5.5 V, VI = 7 V 2
High-level input current IIH 20 µA VCC = 5.5 V, VI = 2.7 V 2
Low-level input current IIL -0.6 mA VCC = 5.5 V, VI = 0.5 V 2
High-level output current IOH 250 µA VCC = 4.5 V 2
Supply current, outputs high ICCH 4 7 mA VCC = 5.5 V, VI = 0 2
Supply current, outputs low ICCL 22 30 mA VCC = 5.5 V, VI = 4.5 V 2
Propagation delay time, low-to-high level output (A or B to Y) tPLH 6.7 13 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay time, low-to-high level output (A or B to Y) tPLH 6.7 9.6 12.5 ns VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C 3
Propagation delay time, high-to-low level output (A or B to Y) tPHL 1 5.5 ns VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX 3
Propagation delay time, high-to-low level output (A or B to Y) tPHL 1 2.6 5 ns VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C 3

CAD (KiCad official)

  • Symbol: SN74F38DR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74f38dr-etched.step / sn74f38dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74f38dr.step / sn74f38dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 75f94a914cc8872e, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF