component

RS595SXTSS16

Public Made by Adom

by adom

Jiangsu RUNIC Tech Shift Registers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentlogicrs595sxtss16factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

RS595SXTSS16

Jiangsu RUNIC Tech · Shift Registers · TSSOP-16

RS595SXTSS16 from Jiangsu RUNIC Tech, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Parallel data output Q1 (8-bit storage register output); VOH ≥3.7 V at IO=−6 mA, VCC=4.5 V; VOL ≤0.4 V at IO=6 mA, VCC=4.5 V; propagation delay from RCLK ≤18 ns at VCC=4.5 V.
2 Q2 output Parallel data output Q2 (8-bit storage register output); VOH ≥3.7 V at IO=−6 mA, VCC=4.5 V; VOL ≤0.4 V at IO=6 mA, VCC=4.5 V; propagation delay from RCLK ≤18 ns at VCC=4.5 V.
3 Q3 output Parallel data output Q3 (8-bit storage register output); VOH ≥3.7 V at IO=−6 mA, VCC=4.5 V; VOL ≤0.4 V at IO=6 mA, VCC=4.5 V; propagation delay from RCLK ≤18 ns at VCC=4.5 V.
4 Q4 output Parallel data output Q4 (8-bit storage register output); VOH ≥3.7 V at IO=−6 mA, VCC=4.5 V; VOL ≤0.4 V at IO=6 mA, VCC=4.5 V; propagation delay from RCLK ≤18 ns at VCC=4.5 V.
5 Q5 output Parallel data output Q5 (8-bit storage register output); VOH ≥3.7 V at IO=−6 mA, VCC=4.5 V; VOL ≤0.4 V at IO=6 mA, VCC=4.5 V; propagation delay from RCLK ≤18 ns at VCC=4.5 V.
6 Q6 output Parallel data output Q6 (8-bit storage register output); VOH ≥3.7 V at IO=−6 mA, VCC=4.5 V; VOL ≤0.4 V at IO=6 mA, VCC=4.5 V; propagation delay from RCLK ≤18 ns at VCC=4.5 V.
7 Q7 output Parallel data output Q7 (8-bit storage register output); VOH ≥3.7 V at IO=−6 mA, VCC=4.5 V; VOL ≤0.4 V at IO=6 mA, VCC=4.5 V; propagation delay from RCLK ≤18 ns at VCC=4.5 V.
8 GND power_in Ground reference; IGND absolute maximum −70 mA.
9 Q7S output Serial data output for cascading shift registers; propagation delay from SRCLK ≤18 ns at VCC=4.5 V; MR-to-Q7S tPHL ≤14 ns at VCC=4.5 V; output current ±25 mA absolute maximum.
10 /MR input Master reset (active Low); asynchronously clears shift register when held Low; minimum pulse width 22 ns at VCC=4.5 V; recovery time to SRCLK ≥15 ns at VCC=4.5 V.
11 SRCLK input Shift register clock input; data shifts into stage 0 on LOW-to-HIGH transition; minimum pulse width High or Low 22 ns at VCC=4.5 V; maximum frequency 20 MHz at VCC=4.5 V, CL=15 pF.
12 RCLK input Storage register clock input; shift register contents transferred to storage register and parallel outputs on LOW-to-HIGH transition; minimum pulse width 22 ns at VCC=4.5 V; setup time from SRCLK ≥22 ns at VCC=4.5 V.
13 /OE input Output enable input (active Low); High forces Q0-Q7 to high-impedance OFF-state without affecting register contents; enable time ≤16 ns, disable time ≤41 ns at VCC=4.5 V.
14 SER input Serial data input to shift register stage 0; setup time to SRCLK ≥15 ns, hold time ≥3 ns at VCC=4.5 V; input leakage ±1 μA max at VCC=5.5 V.
15 Q0 output Parallel data output Q0 (8-bit storage register output, LSB); VOH ≥3.7 V at IO=−6 mA, VCC=4.5 V; VOL ≤0.4 V at IO=6 mA, VCC=4.5 V; propagation delay from RCLK ≤18 ns at VCC=4.5 V.
16 VCC power_in Supply voltage; recommended operating range 2 V to 5.5 V; ICC ≤160 μA (max) at VCC=5.5 V, IO=0 A; absolute maximum 6.5 V.

Key specifications

Parameter Value
Manufacturer Jiangsu RUNIC Tech
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: RS595SXTSS16
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: rs595sxtss16-etched.step / rs595sxtss16-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rs595sxtss16.step / rs595sxtss16.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Jiangsu RUNIC Tech datasheet (19 pp, sha256 06c9bb29e6da6d97, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF