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TMI6050-33

Public Made by Adom

by adom

TMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TMI6050-33

TMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5

TMI6050-33 from TMI, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input supply of the LDO. Operating range 2.5V to 5.5V (absolute max 6V). Requires a >=1µF X5R/X7R ceramic bypass capacitor placed close to the pin.
2 GND power_in Signal ground reference for the LDO. Return path for both input and output capacitors.
3 EN input Active-high enable input. Drive to <=0.4V (VENL max 0.85V) to disable the device (I_SHDN <1µA typ); drive to >=1.05V (VENH max 1.15V) to enable. Must not be left floating. EN input current is ~0.2µA (VIN=VEN=3.5V). Absolute max = -0.3V to 6V.
4 NC unconnected No connect on the fixed-output version (TMI6050-33). Internal feedback network sets the output to 3.3V; this pin has no external function and may be left open.
5 VOUT power_out Regulated 3.3V output of the LDO. Up to 600mA typical output current, ±2% accuracy, 600mV typ dropout at 600mA. Requires a 1µF-10µF X5R/X7R ceramic output capacitor for stability. Internally auto-discharged via ~130Ω resistor to GND when the regulator is disabled. Short-circuit protection clamps output current to ~150mA when VOUT is pulled to GND.

Key specifications

Parameter Value
Manufacturer TMI
Package SOT-23-5
Category PMIC
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • TMI6050-33
  • TMI6050-33TEGXXX
  • TMI6050B-33
  • TMI6050-33TGGXXX

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN, EN input voltage range -0.3 6 V 2
All other pins voltage range -0.3 V Printed maximum is VIN+0.3 (expression, not computed) 2
Junction temperature 160 °C 2
Storage temperature range -65 150 °C 2
Junction-to-ambient thermal resistance 120 °C/W Note 1: 3cm x 5cm 2-layer FR-4 board, 1oz copper 2
Junction-to-ambient thermal resistance 220 °C/W Note 2: 2cm x 2cm 2-layer small FR-4 board, 1oz copper, no via holes on GND copper 2
Junction-to-board thermal resistance 36 °C/W Note 1 2
Junction-to-case (top) thermal resistance 62 °C/W Note 1 2
Junction-to-top characterization parameter 11 °C/W Note 1 2
Junction-to-board characterization parameter 39.5 °C/W Note 1 2
Power dissipation 1.1 W Note 1 2
Power dissipation 0.6 W Note 2 2
Lead temperature soldering 260 °C 10 sec 2
ESD Human Body Model (all pins) VESD_HBM -2000 2000 V ESDA/JEDEC JS-002 2
ESD Charged Device Model (all pins) VESD_CDM -2000 2000 V ESDA/JEDEC JS-002 2
Voltage range IN IN 2.5 5.5 V 2
TJ operation junction temperature TJ -40 125 °C 2
Input voltage range VIN 2.5 5.5 V 5
Quiescent current IQ 75 90 μA VEN=2.5V, IOUT=0mA 5
Shutdown current ISHDN 0.1 1 μA VEN=0V 5
Power supply ripple rejection PSRR 60 dB VIN=Vnom+1VP-P, f=1kHz, ILOAD=10mA 5
EN rising threshold VENH 0.7 0.9 1.15 V All temperature range 5
EN falling threshold VENL 0.45 0.6 0.85 V All temperature range 5
EN input current IEN -1 0.2 1 μA VIN=3.5V, VEN=3.5V or 0V 5
Start-up time TST 40 μs VIN=3.5V, VOUT=2.5V 5
Output voltage accuracy VOUT -2 2 % VIN=VOUT+1V, IOUT=10mA 5
Output voltage accuracy over temperature VOUT -3 3 % VIN=VOUT+1V, IOUT=10mA, TA=-40°C to +85°C 5
Output line regulation VLNR 0.01 0.1 %/V VOUT+0.5V<VIN<5.5V, IOUT=10mA 5
Output load regulation VLDR 12 mV 2mA<IOUT<600mA, VIN=VNOM+1.0V 5
Dropout voltage VDROP 600 700 mV IOUT=600mA 5
Maximum output current IOUTMAX 600 mA VIN=VOUT+1V 5
Current limit Ilimit 650 800 mA 5
Output short current limit Ishort 150 mA VFB or VOUT = 0V 5
Resistance of auto-discharge RAD 130 Ω 5
Thermal shutdown temperature TSD 160 °C No load, VIN=VEN=5V 5
Thermal shutdown hysteresis TSDHYS 20 °C No load, VIN=VEN=5V 5

CAD (KiCad official)

  • Symbol: TMI6050-33
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tmi6050-33-etched.step / tmi6050-33-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tmi6050-33.step / tmi6050-33.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
tmi6050-33.step 85 KB You want the bare part, or you mark your own boards.
tmi6050-33-etched.step 2.1 MB You want the part with TMI6050-33 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 500 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TMI datasheet (12 pp, sha256 27c3f99ed549b2f6, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF