component
DRV8703DQRHBRQ1
Public Made by Adomby adom
Texas Instruments Motor Driver ICs, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8703DQRHBRQ1
Texas Instruments · Motor Driver ICs · VQFN-32-EP(5x5)
DRV8703DQRHBRQ1 from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground; connect this pin to the system ground. |
| 2 | IN1 | input | Input control pin whose logic depends on the MODE pin; it has an internal pulldown resistor. |
| 3 | IN2 | input | Input control pin whose logic depends on the MODE pin; it has an internal pulldown resistor. |
| 4 | SDO | output | SPI output signal; open-drain output that requires an external pullup resistor. |
| 5 | nSCS | input | SPI chip select, active low, serving as the select and enable for SPI; it has an internal pulldown resistor. |
| 6 | SDI | input | SPI input signal; it has an internal pulldown resistor. |
| 7 | SCLK | input | SPI clock signal; it has an internal pulldown resistor. |
| 8 | nSLEEP | input | Pull to logic low to place the device in low-power sleep mode with the FETs in high impedance (Hi-Z); it has an internal pulldown resistor. |
| 9 | nWDFLT | output | Watchdog fault indication; pulled logic low when a watchdog fault occurs and requires an external pullup resistor (open-drain). |
| 10 | nFAULT | output | Fault indication; pulled logic low when a fault condition occurs and requires an external pullup resistor (open-drain). |
| 11 | MODE | input | Mode control; pull to logic high for half-bridge operation without internal current regulation, or leave as no-connect for operation with current regulation, latched on power-up or on exiting sleep mode. |
| 12 | DVDD | power_out | Logic regulator for the 3.3-V logic supply; bypass to ground with a 6.3-V, 1-µF ceramic capacitor. |
| 13 | GND | power_in | Device ground; connect this pin to the system ground. |
| 14 | AVDD | power_out | 5-V analog supply regulator output; bypass to ground with a 6.3-V, 1-µF ceramic capacitor. |
| 15 | VREF | power_in | Current set reference input; the voltage on this pin sets the driver chopping current. |
| 16 | SO | output | Shunt-amplifier output equal to the SP voltage times AV plus an offset; place no more than 1 nF of capacitance on this pin. |
| 17 | GND | power_in | Device ground; connect this pin to the system ground. |
| 18 | GH | output | High-side gate; connect this pin to the high-side FET gate. |
| 19 | SH | input | High-side source; connect this pin to the high-side FET source. |
| 20 | GL | output | Low-side gate; connect this pin to the low-side FET gate. |
| 21 | SP | input | Shunt-amplifier positive input; connect this pin to the current-sense resistor. |
| 22 | SN | input | Shunt-amplifier negative input; connect this pin to the current-sense resistor. |
| 23 | SP | input | Shunt-amplifier positive input; connect this pin to the current-sense resistor. |
| 24 | RSVD | unconnected | Reserved; do not connect anything. |
| 25 | GND | power_in | Device ground; connect this pin to the system ground. |
| 26 | RSVD | unconnected | Reserved; do not connect anything. |
| 27 | VDRAIN | input | High-side FET drain connection, common for the half-bridge; absolute maximum drain pin voltage is 47 V. |
| 28 | VM | power_in | Power supply; connect to the motor supply voltage, bypassed with 0.1-µF ceramic plus 10-µF (minimum) capacitance; operating range 5.5 V to 45 V. |
| 29 | VCP | power_out | Charge-pump output; connect a 16-V, 1-µF ceramic capacitor between this pin and the VM pin. |
| 30 | CPH | passive | Charge-pump switching node; connect a 0.1-µF X7R capacitor rated for the supply voltage (VM) between CPH and CPL. |
| 31 | CPL | passive | Charge-pump switching node; connect a 0.1-µF X7R capacitor rated for the supply voltage (VM) between CPH and CPL. |
| 32 | NC | unconnected | No connect; no internal connection. |
| 33 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
DRV8703DQRHBRQ1 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
drv8703dqrhbrq1-etched.step/drv8703dqrhbrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8703dqrhbrq1.step/drv8703dqrhbrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (62 pp, sha256
33ef2709c2672200, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).