component
CD40174BNSR
Public Made by Adomby adom
Texas Instruments Flip Flops, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD40174BNSR
Texas Instruments · Flip Flops · SO-16
CD40174BNSR from Texas Instruments, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLEAR | input | Active-low asynchronous clear common to all six flip-flops; a low level resets all Q outputs simultaneously. |
| 2 | Q1 | output | Q output of flip-flop 1, updated on the positive-going clock transition. |
| 3 | D1 | input | Data input of flip-flop 1, transferred to Q1 on the positive-going clock edge. |
| 4 | D2 | input | Data input of flip-flop 2, transferred to Q2 on the positive-going clock edge. |
| 5 | Q2 | output | Q output of flip-flop 2, updated on the positive-going clock transition. |
| 6 | D3 | input | Data input of flip-flop 3, transferred to Q3 on the positive-going clock edge. |
| 7 | Q3 | output | Q output of flip-flop 3, updated on the positive-going clock transition. |
| 8 | VSS | power_in | Ground/negative supply terminal; all voltage ratings are referenced to VSS. |
| 9 | CLOCK | input | Clock input common to all six flip-flops; data transfers to Q on the positive-going transition, max clock frequency 3.5/6/8 MHz at 5/10/15 V. |
| 10 | Q4 | output | Q output of flip-flop 4, updated on the positive-going clock transition. |
| 11 | D4 | input | Data input of flip-flop 4, transferred to Q4 on the positive-going clock edge. |
| 12 | Q5 | output | Q output of flip-flop 5, updated on the positive-going clock transition. |
| 13 | D5 | input | Data input of flip-flop 5, transferred to Q5 on the positive-going clock edge. |
| 14 | D6 | input | Data input of flip-flop 6, transferred to Q6 on the positive-going clock edge. |
| 15 | Q6 | output | Q output of flip-flop 6, updated on the positive-going clock transition. |
| 16 | VDD | power_in | Positive supply; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD40174BNSR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
cd40174bnsr-etched.step/cd40174bnsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd40174bnsr.step/cd40174bnsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
ca2dc4be7c5d3e2a, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).