Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SN74ACT244DBR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SSOP-20-208mil

SN74ACT244DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for the first buffer section; when high, outputs 1Y1 to 1Y4 are placed in the high-impedance state.
2 1A1 input Data input 1A1 of the first buffer section; inputs accept voltages up to 5.5 V and are TTL compatible.
3 2Y4 output Non-inverting 3-state output 2Y4 of the second buffer section, high-impedance when 2OE is high.
4 1A2 input Data input 1A2 of the first buffer section; inputs accept voltages up to 5.5 V and are TTL compatible.
5 2Y3 output Non-inverting 3-state output 2Y3 of the second buffer section, high-impedance when 2OE is high.
6 1A3 input Data input 1A3 of the first buffer section; inputs accept voltages up to 5.5 V and are TTL compatible.
7 2Y2 output Non-inverting 3-state output 2Y2 of the second buffer section, high-impedance when 2OE is high.
8 1A4 input Data input 1A4 of the first buffer section; inputs accept voltages up to 5.5 V and are TTL compatible.
9 2Y1 output Non-inverting 3-state output 2Y1 of the second buffer section, high-impedance when 2OE is high.
10 GND power_in Ground reference for the device.
11 2A1 input Data input 2A1 of the second buffer section; inputs accept voltages up to 5.5 V and are TTL compatible.
12 1Y4 output Non-inverting 3-state output 1Y4 of the first buffer section, high-impedance when 1OE is high.
13 2A2 input Data input 2A2 of the second buffer section; inputs accept voltages up to 5.5 V and are TTL compatible.
14 1Y3 output Non-inverting 3-state output 1Y3 of the first buffer section, high-impedance when 1OE is high.
15 2A3 input Data input 2A3 of the second buffer section; inputs accept voltages up to 5.5 V and are TTL compatible.
16 1Y2 output Non-inverting 3-state output 1Y2 of the first buffer section, high-impedance when 1OE is high.
17 2A4 input Data input 2A4 of the second buffer section; inputs accept voltages up to 5.5 V and are TTL compatible.
18 1Y1 output Non-inverting 3-state output 1Y1 of the first buffer section, high-impedance when 1OE is high.
19 2OE input Active-low output enable for the second buffer section; when high, outputs 2Y1 to 2Y4 are placed in the high-impedance state.
20 VCC power_in Power supply; recommended operating range is 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-208mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
Input voltage VI 0 V maximum printed as VCC 4
Output voltage VO 0 V maximum printed as VCC 4
High-level output current IOH -24 mA 4
Low-level output current IOL 24 mA 4
Input transition rise or fall rate Δt/Δv 8 ns/V 4
Operating free-air temperature (SN74ACT244) TA -40 85 °C 4
Supply voltage VCC -0.5 7 V 4
Input voltage VI -0.5 V maximum printed as VCC + 0.5 V 4
Output voltage VO -0.5 V maximum printed as VCC + 0.5 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -50 50 mA VO = 0 to VCC 4
Continuous current through VCC or GND -200 200 mA 4
Absolute maximum junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
VOH high-level output voltage VOH 4.4 V IOH = -50 µA, VCC = 4.5 V 5
VOH high-level output voltage VOH 5.4 V IOH = -50 µA, VCC = 5.5 V 5
VOH high-level output voltage VOH 3.76 V IOH = -24 mA, VCC = 4.5 V 5
VOH high-level output voltage VOH 4.76 V IOH = -24 mA, VCC = 5.5 V 5
VOH high-level output voltage VOH 3.85 V IOH = -75 mA, VCC = 5.5 V 5
VOL low-level output voltage VOL 0.1 V IOL = 50 µA, VCC = 4.5 V 5
VOL low-level output voltage VOL 0.44 V IOL = 24 mA, VCC = 4.5 V 5
VOL low-level output voltage VOL 1.65 V IOL = 75 mA, VCC = 5.5 V 5
Off-state output current (high-impedance) IOZ -2.5 2.5 µA VO = VCC or GND, VCC = 5.5 V 5
Input current II -1 1 µA VI = VCC or GND, VCC = 5.5 V 6
Quiescent supply current ICC 40 µA VI = VCC or GND, IO = 0, VCC = 5.5 V 6
Supply current increase per TTL-level input ΔICC 1.5 mA One input at 3.4 V, other inputs at GND or VCC, VCC = 5.5 V 6
Propagation delay A to Y (low-to-high) tPLH 1.5 10 ns From A to Y, VCC = 5 V ± 0.5 V (see Figure 2) 6
Propagation delay A to Y (high-to-low) tPHL 1.5 10 ns From A to Y, VCC = 5 V ± 0.5 V (see Figure 2) 6
Output enable time OE to Y (high) tPZH 1 9.5 ns From OE to Y, VCC = 5 V ± 0.5 V (see Figure 2) 6
Output enable time OE to Y (low) tPZL 1.5 10.5 ns From OE to Y, VCC = 5 V ± 0.5 V (see Figure 2) 6
Output disable time OE to Y (high) tPHZ 1.5 10.5 ns From OE to Y, VCC = 5 V ± 0.5 V (see Figure 2) 6
Output disable time OE to Y (low) tPLZ 2 10.5 ns From OE to Y, VCC = 5 V ± 0.5 V (see Figure 2) 6
Propagation delay A to Y (low-to-high), 25 °C tPLH 2 9 ns TA = 25°C, VCC = 5 V ± 0.5 V (see Figure 2) 6
Propagation delay A to Y (high-to-low), 25 °C tPHL 2 9 ns TA = 25°C, VCC = 5 V ± 0.5 V (see Figure 2) 6
Output enable time OE to Y (high), 25 °C tPZH 1.5 8.5 ns TA = 25°C, VCC = 5 V ± 0.5 V (see Figure 2) 6
Output enable time OE to Y (low), 25 °C tPZL 2 9.5 ns TA = 25°C, VCC = 5 V ± 0.5 V (see Figure 2) 6
Output disable time OE to Y (high), 25 °C tPHZ 2 9.5 ns TA = 25°C, VCC = 5 V ± 0.5 V (see Figure 2) 6
Output disable time OE to Y (low), 25 °C tPLZ 2.5 10 ns TA = 25°C, VCC = 5 V ± 0.5 V (see Figure 2) 6
Junction-to-ambient thermal resistance (DB, SSOP) RθJA 94.1 °C/W DB (SSOP) package, 20 pins 5
Junction-to-case (top) thermal resistance (DB, SSOP) RθJC(top) 55.6 °C/W DB (SSOP) package, 20 pins 5
Junction-to-board thermal resistance (DB, SSOP) RθJB 49.3 °C/W DB (SSOP) package, 20 pins 5
Junction-to-top characterization parameter (DB, SSOP) ψJT 20.8 °C/W DB (SSOP) package, 20 pins 5
Junction-to-board characterization parameter (DB, SSOP) ψJB 48.9 °C/W DB (SSOP) package, 20 pins 5

CAD (KiCad official)

  • Symbol: SN74ACT244DBR
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74act244dbr-etched.step / sn74act244dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act244dbr.step / sn74act244dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 2ca98aa41e817cba, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF