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MC74HCT541ADTR2G

Public Made by Adom

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onsemi Buffers / Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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MC74HCT541ADTR2G

onsemi · Buffers / Drivers · TSSOP-20

MC74HCT541ADTR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low output enable; when both OE1 and OE2 are low the outputs are enabled, and a high on either puts the outputs in high impedance.
2 A1 input Data input 1; appears non-inverted on Y1 when outputs are enabled.
3 A2 input Data input 2; appears non-inverted on Y2 when outputs are enabled.
4 A3 input Data input 3; appears non-inverted on Y3 when outputs are enabled.
5 A4 input Data input 4; appears non-inverted on Y4 when outputs are enabled.
6 A5 input Data input 5; appears non-inverted on Y5 when outputs are enabled.
7 A6 input Data input 6; appears non-inverted on Y6 when outputs are enabled.
8 A7 input Data input 7; appears non-inverted on Y7 when outputs are enabled.
9 A8 input Data input 8; appears non-inverted on Y8 when outputs are enabled.
10 GND power_in Ground pin (0 V reference) for the device.
11 Y8 tri_state Non-inverting 3-state output 8, high impedance when either output enable is high.
12 Y7 tri_state Non-inverting 3-state output 7, high impedance when either output enable is high.
13 Y6 tri_state Non-inverting 3-state output 6, high impedance when either output enable is high.
14 Y5 tri_state Non-inverting 3-state output 5, high impedance when either output enable is high.
15 Y4 tri_state Non-inverting 3-state output 4, high impedance when either output enable is high.
16 Y3 tri_state Non-inverting 3-state output 3, high impedance when either output enable is high.
17 Y2 tri_state Non-inverting 3-state output 2, high impedance when either output enable is high.
18 Y1 tri_state Non-inverting 3-state output 1, high impedance when either output enable is high.
19 OE2 input Active-low output enable; when both OE1 and OE2 are low the outputs are enabled, and a high on either puts the outputs in high impedance.
20 VCC power_in Positive supply voltage, recommended 4.5 to 5.5 V (absolute maximum -0.5 to +7.0 V).

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC 4.5 5.5 V Referenced to GND 2
Operating Temperature Range TA -55 125 °C All Package Types 2
Input Rise/Fall Time tr, tf 0 500 ns Figure 1 2
DC Supply Voltage VCC -0.5 7 V Referenced to GND 2
DC Input Voltage Vin -0.5 5.5 V -0.5 to VCC + 0.5 V, referenced to GND (max shown at VCC=5.0 V) 2
DC Input Current per Pin Iin -20 20 mA 2
DC Output Current per Pin Iout -35 35 mA 2
DC Supply Current, VCC and GND Pins ICC -75 75 mA 2
Storage Temperature Range Tstg -65 150 °C 2
Minimum High-Level Input Voltage VIH 2 V Vout = 0.1V or VCC-0.1V, /Iout/ ≤ 20µA, VCC 4.5-5.5 V, all temps 2
Maximum Low-Level Input Voltage VIL 0.8 V Vout = 0.1V or VCC-0.1V, /Iout/ ≤ 20µA, VCC 4.5-5.5 V, all temps 2
Minimum High-Level Output Voltage, -55 to 25°C VOH 4.4 V Vin = VIH or VIL, /Iout/ ≤ 20µA, VCC=4.5 V 2
Minimum High-Level Output Voltage, -55 to 25°C VOH 3.98 V Vin = VIH or VIL, /Iout/ ≤ 6.0mA, VCC=4.5 V 2
Minimum High-Level Output Voltage, ≤85°C VOH 3.84 V Vin = VIH or VIL, /Iout/ ≤ 6.0mA, VCC=4.5 V 2
Minimum High-Level Output Voltage, ≤125°C VOH 3.7 V Vin = VIH or VIL, /Iout/ ≤ 6.0mA, VCC=4.5 V 2
Maximum Low-Level Output Voltage VOL 0.1 V Vin = VIH or VIL, /Iout/ ≤ 20µA, VCC 4.5-5.5 V, all temps 2
Maximum Low-Level Output Voltage, -55 to 25°C VOL 0.26 V Vin = VIH or VIL, /Iout/ ≤ 6.0mA, VCC=4.5 V 2
Maximum Low-Level Output Voltage, ≤85°C VOL 0.33 V Vin = VIH or VIL, /Iout/ ≤ 6.0mA, VCC=4.5 V 2
Maximum Low-Level Output Voltage, ≤125°C VOL 0.4 V Vin = VIH or VIL, /Iout/ ≤ 6.0mA, VCC=4.5 V 2
Maximum Input Leakage Current, -55 to 25°C Iin -0.1 0.1 µA Vin = VCC or GND, VCC=5.5 V 2
Maximum Input Leakage Current, ≤85°C and ≤125°C Iin -1 1 µA Vin = VCC or GND, VCC=5.5 V 2
Maximum 3-State Leakage Current, -55 to 25°C IOZ -0.5 0.5 µA Output in High Impedance State, Vin = VIL or VIH, Vout = VCC or GND, VCC=5.5 V 2
Maximum 3-State Leakage Current, ≤85°C IOZ -5 5 µA Output in High Impedance State, Vin = VIL or VIH, Vout = VCC or GND, VCC=5.5 V 2
Maximum 3-State Leakage Current, ≤125°C IOZ -10 10 µA Output in High Impedance State, Vin = VIL or VIH, Vout = VCC or GND, VCC=5.5 V 2
Maximum Quiescent Supply Current, -55 to 25°C ICC 4 µA Vin = VCC or GND, Iout = 0A, VCC=5.5 V 2
Maximum Quiescent Supply Current, ≤85°C ICC 40 µA Vin = VCC or GND, Iout = 0A, VCC=5.5 V 2
Maximum Quiescent Supply Current, ≤125°C ICC 160 µA Vin = VCC or GND, Iout = 0A, VCC=5.5 V 2
Additional Quiescent Supply Current, ≥ -55°C ΔICC 2.9 mA Vin = 2.4V, Any One Input, other inputs VCC or GND, Iout = 0A, VCC=5.5 V 2
Additional Quiescent Supply Current, 25 to 125°C ΔICC 2.4 mA Vin = 2.4V, Any One Input, other inputs VCC or GND, Iout = 0A, VCC=5.5 V 2
Max Propagation Delay, Input A to Output Y, -55 to 25°C tPLH, tPHL 23 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Propagation Delay, Input A to Output Y, ≤85°C tPLH, tPHL 28 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Propagation Delay, Input A to Output Y, ≤125°C tPLH, tPHL 32 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Propagation Delay, Output Enable to Output Y (disable), -55 to 25°C tPLZ, tPHZ 30 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Propagation Delay, Output Enable to Output Y (disable), ≤85°C tPLZ, tPHZ 34 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Propagation Delay, Output Enable to Output Y (disable), ≤125°C tPLZ, tPHZ 38 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Propagation Delay, Output Enable to Output Y (enable), -55 to 25°C tPZL, tPZH 30 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Propagation Delay, Output Enable to Output Y (enable), ≤85°C tPZL, tPZH 34 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Propagation Delay, Output Enable to Output Y (enable), ≤125°C tPZL, tPZH 38 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Output Transition Time, -55 to 25°C tTLH, tTHL 12 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Output Transition Time, ≤85°C tTLH, tTHL 15 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Max Output Transition Time, ≤125°C tTLH, tTHL 18 ns VCC = 5.0V, CL = 50 pF, tr = tf = 6 ns 3
Maximum Input Capacitance Cin 10 pF All temperature columns 3
Maximum 3-State Output Capacitance Cout 15 pF Output in High Impedance State, all temperature columns 3
Power Dissipation Capacitance (Per Buffer) CPD 55 pF Typical @ 25°C, VCC = 5.0 V 3

CAD (KiCad official)

  • Symbol: MC74HCT541ADTR2G
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: mc74hct541adtr2g-etched.step / mc74hct541adtr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mc74hct541adtr2g.step / mc74hct541adtr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (7 pp, sha256 62e83a609a41e5f0, retrieved 2026-10-22, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF