component
TPL720F33-3TR
Public Made by Adomby adom
3PEAK Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPL720F33-3TR
3PEAK · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3
TPL720F33-3TR from 3PEAK, in a SOT-23-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin; connect GND directly to the PCB ground plane. |
| 2 | OUT | power_out | Regulated output voltage pin; bypass OUT to GND with a 2.2 µF or greater capacitor. |
| 3 | IN | power_in | Input voltage pin (recommended VIN range 2.4 V to 6 V); bypass IN to GND with a 1 µF or greater capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 3PEAK |
| Package | SOT-23-3 |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.4 | 6 | V | 7 | ||
| Output current | IOUT | 0 | 400 | mA | VOUT in regulation | 7 | |
| Output current limit | ICL | 410 | 560 | 800 | mA | VOUT = 0.9 × VOUT(NOM) | 7 |
| Output voltage accuracy (room temperature) | VOUT | -1 | 1 | % | IOUT = 30 mA, TJ = +25°C | 7 | |
| Output voltage accuracy (over temperature) | VOUT | -3 | 3 | % | IOUT = 30 mA, -40°C ≤ TJ ≤ +125°C | 7 | |
| Input voltage (VIN, VEN) absolute maximum | VIN, VEN | -0.3 | 6.5 | V | 6 | ||
| Output voltage absolute maximum | VOUT | -0.3 | 6.5 | V | 6 | ||
| Junction temperature range (absolute maximum) | TJ | -40 | 150 | °C | 6 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 6 | ||
| Lead temperature (soldering 10 sec) | TL | 260 | °C | 10 sec soldering | 6 | ||
| Input voltage | VIN | 2.4 | 6 | V | 6 | ||
| Enable voltage | VEN | 0 | V | 6 | |||
| Output voltage | VOUT | 0 | 5 | V | 6 | ||
| Output current | IOUT | 0 | 400 | mA | 6 | ||
| Operating junction temperature range | TJ | -40 | 125 | °C | 6 | ||
| Operating ambient temperature range | TA | -40 | 85 | °C | 6 | ||
| Ground pin current | IGND | 1.4 | µA | IOUT = 0 mA | 7 | ||
| Ground pin current | IGND | 2.8 | µA | IOUT = 1 mA | 7 | ||
| VIN under-voltage lock-out (rising) | UVLO | 1.8 | V | VIN rising | 7 | ||
| VIN under-voltage lock-out hysteresis | 200 | mV | 7 | ||||
| Line regulation | ΔVOUT | 3 | mV | VIN = VOUT(NOM) + 2 V to 6 V, or VIN ≥ 2.4V, IOUT = 1 mA | 7 | ||
| Load regulation | 40 | mV | IOUT = 1 mA to 400 mA | 7 | |||
| Dropout voltage | VDO | 80 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 100 mA | 7 | ||
| Dropout voltage | VDO | 170 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 200 mA | 7 | ||
| Dropout voltage | VDO | 350 | mV | VIN = 0.98 × VOUT(NOM), IOUT = 400 mA | 7 | ||
| Power supply rejection ratio | PSRR | 55 | dB | IOUT = 10 mA, f = 100 Hz, COUT = 2.2 µF | 7 | ||
| Power supply rejection ratio | PSRR | 54 | dB | IOUT = 10 mA, f = 1 kHz, COUT = 2.2 µF | 7 | ||
| Power supply rejection ratio | PSRR | 50 | dB | IOUT = 10 mA, f = 10 kHz, COUT = 2.2 µF | 7 | ||
| Power supply rejection ratio | PSRR | 53 | dB | IOUT = 10 mA, f = 1 MHz, COUT = 2.2 µF | 7 | ||
| Output noise voltage | VN | 90 | µVRMS | IOUT = 10 mA, BW = 10Hz to 100 kHz | 7 | ||
| Thermal shutdown temperature | TSD | 165 | ºC | 7 | |||
| Thermal shutdown hysteresis | 15 | ºC | 7 | ||||
| Junction-to-ambient thermal resistance, SOT23-3 | θJA | 280 | °C/W | SOT23-3 package | 6 | ||
| Junction-to-case thermal resistance, SOT23-3 | θJC | 62 | °C/W | SOT23-3 package | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | capacitor connection, IN pin and the GND pin of the system must be as small as possible. • It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipation. | 13 |
CAD (KiCad official)
- Symbol:
TPL720F33-3TR - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3 (KiCad packages3D, STEP)
- 3D model files:
tpl720f33-3tr-etched.step/tpl720f33-3tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tpl720f33-3tr.step/tpl720f33-3tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 3PEAK datasheet (18 pp, sha256
c65dff82814441be, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).