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AGRV2KL48

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AGM Microelectronics Programmable Logic Device (CPLDs/FPGAs), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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PCB Footprint

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Datasheet

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Contents

README

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AGRV2KL48

AGM Microelectronics · Programmable Logic Device (CPLDs/FPGAs) · LQFP-48(7x7)

AGRV2KL48 from AGM Microelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD33 power_in 3.3-V supply pin; the power-on reset circuit monitors VDD33 to begin SRAM download.
2 IO_GB/PIN_2 bidirectional Dual-purpose general I/O (3.3-V LVCMOS/LVTTL) that can also serve as a dedicated global clock input.
3 NC unconnected No connect.
4 NC unconnected No connect.
5 NC unconnected No connect.
6 NC unconnected No connect.
7 NRST input Reset pin of the device.
8 GND power_in Ground.
9 VDD33 power_in 3.3-V supply pin.
10 IO/PIN_10 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
11 IO/PIN_11 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
12 IO/PIN_12 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
13 IO/PIN_13 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
14 IO/PIN_14 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
15 IO/PIN_15 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
16 IO/PIN_16 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
17 IO/PIN_17 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
18 IO/PIN_18 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
19 IO/PIN_19 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
20 IO/PIN_20 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
21 IO/PIN_21 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
22 IO/PIN_22 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
23 GND power_in Ground.
24 VDD33 power_in 3.3-V supply pin.
25 IO/PIN_25 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
26 IO/PIN_26 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
27 IO/PIN_27 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
28 IO/PIN_28 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
29 IO/PIN_29 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
30 IO/PIN_30 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
31 IO/PIN_31 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
32 IO/PIN_32 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
33 IO/PIN_33 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
34 TMS input JTAG test mode select pin (IEEE 1149.1), 3.3-V I/O standard.
35 IO/PIN_35 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
36 VDD33 power_in 3.3-V supply pin.
37 TCK input JTAG test clock pin (IEEE 1149.1), 3.3-V I/O standard.
38 IO/PIN_38 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
39 IO/PIN_39 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
40 IO/PIN_40 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
41 IO/PIN_41 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
42 IO/PIN_42 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
43 IO/PIN_43 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
44 GND power_in Ground.
45 IO/PIN_45 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
46 IO/PIN_46 bidirectional General-purpose user I/O supporting 3.3-V LVCMOS and LVTTL.
47 GND power_in Ground.
48 VDD33 power_in 3.3-V supply pin.

Key specifications

Parameter Value
Manufacturer AGM Microelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
SLICE Combinatorial LUT Delay TLUT 1.111 ns 9
SLICE Register Clear Delay TCLR 0.032 ns 9
SLICE Register Preset Delay TPRE 0.408 ns 9
SLICE Register Setup TSU 0.664 ns 9
SLICE Register Hold TH -0.636 ns 9
SLICE Register Clock-To-Output Delay TCO 0.455 ns 9
Minimum Clock High or Low Time TCLKHL 0.3 ns 9
I/O Input Pad and Buffer Delay TIN 0.767 1.308 ns 9
Output Delay Buffer and Pad Delay TDO 1.421 2.14 ns 9
Output Buffer Disable Delay TXZ 0.867 1.322 ns 9
Output Buffer Enable Delay TZX 1.242 1.532 ns 9
Delay for a column interconnect with average loading TC 0.679 ns 9
Delay for a row interconnect with average loading TR 0.523 ns 9
Local Routing Delay TLOCAL 0.434 ns 9
Operating junction temperature -40 85 ℃ 2

CAD (KiCad official)

  • Symbol: AGRV2KL48
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: agrv2kl48-etched.step / agrv2kl48-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); agrv2kl48.step / agrv2kl48.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: AGM Microelectronics datasheet (18 pp, sha256 7747d7cd44b8c59c, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF