Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

MCP4331-103E

Microchip Tech · Digital Potentiometers · TSSOP-20

MCP4331-103E from Microchip Tech, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P3A passive Potentiometer 3 Terminal A, the full-scale end of the resistor network, which must be held between VSS and VDD.
2 P3W passive Potentiometer 3 wiper terminal, the adjustable terminal, which must be held between VSS and VDD.
3 P3B passive Potentiometer 3 Terminal B, the zero-scale end (wiper value 0x00), which must be held between VSS and VDD.
4 CS input SPI chip select input (high-voltage tolerant, Schmitt trigger, smart weak pull-up); VIL enables serial commands and VIHH enables high-voltage serial commands.
5 SCK input SPI serial clock input (high-voltage tolerant, Schmitt trigger); the device is an SPI slave so this pin is input only.
6 SDI input SPI serial data input (high-voltage tolerant, Schmitt trigger), connected to the host controller's SDO pin.
7 VSS power_in Device ground reference.
8 P1B passive Potentiometer 1 Terminal B, the zero-scale end, which must be held between VSS and VDD.
9 P1W passive Potentiometer 1 wiper terminal, which must be held between VSS and VDD.
10 P1A passive Potentiometer 1 Terminal A, the full-scale end, which must be held between VSS and VDD.
11 P0A passive Potentiometer 0 Terminal A, the full-scale end, which must be held between VSS and VDD.
12 P0W passive Potentiometer 0 wiper terminal, which must be held between VSS and VDD.
13 P0B passive Potentiometer 0 Terminal B, the zero-scale end, which must be held between VSS and VDD.
14 NC unconnected No connect; the pin is not used.
15 RESET input Hardware reset input (high-voltage tolerant, Schmitt trigger, weak pull-up) that forces the device into the POR/BOR state.
16 SDO output SPI serial data output, connected to the host controller's SDI pin, used to read registers or monitor the command error bit.
17 VDD power_in Positive power supply input relative to VSS; device operates from 1.8V to 5.5V, with specifications guaranteed from 2.7V to 5.5V.
18 P2B passive Potentiometer 2 Terminal B, the zero-scale end, which must be held between VSS and VDD.
19 P2W passive Potentiometer 2 wiper terminal, which must be held between VSS and VDD.
20 P2A passive Potentiometer 2 Terminal A, the full-scale end, which must be held between VSS and VDD.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TSSOP-20
Category ADC/DAC/Data Conversion
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Nominal resistance RAB (-103 device) RAB 8 10 12 kΩ -103 devices (Note 1), ±20% 5
Resistance tolerance RAB -20 20 % -103 devices 5
Supply Voltage VDD 2.7 5.5 V 4
Supply Voltage (serial interface only) VDD 1.8 2.7 V Serial Interface only 4
VDD start voltage to ensure wiper reset VBOR 1.65 V RAM retention voltage (VRAM) < VBOR 4
Delay after device exits Reset state TBORD 10 20 µs VDD > VBOR 4
Supply current, serial interface active IDD 450 µA VDD = 5.5V, CS = VIL, SCK @ 5 MHz, write all 0's to volatile Wiper 0 4
Supply current, serial interface inactive IDD 2.5 5 µA CS = VIH, VDD = 5.5V 4
Supply current, serial interface active (high voltage) IDD 0.55 1 mA VDD = 5.5V, CS = VIHH, SCK @ 5 MHz, decrement volatile Wiper 0 4
Nominal resistance match (10k) /RABWC - RABMEAN//RABMEAN 0.2 1.25 % 10 k MCP43X1 devices only 5
RBW match (10k) /RBWWC - RBWMEAN//RBWMEAN 0.25 1.5 % 10 k, Code = Full Scale 5
Wiper resistance (5.5V) RW 75 160 Ω VDD = 5.5 V, IW = 2.0 mA, code = 00h 5
Wiper resistance (2.7V) RW 75 300 Ω VDD = 2.7 V, IW = 2.0 mA, code = 00h 5
Resolution N 129 Taps 7-bit No Missing Codes 5
Nominal resistance tempco ΔRAB/ΔT 50 ppm/°C TA = -20°C to +70°C 5
Nominal resistance tempco ΔRAB/ΔT 100 ppm/°C TA = -40°C to +85°C 5
Nominal resistance tempco ΔRAB/ΔT 150 ppm/°C TA = -40°C to +125°C 5
Ratiometric tempco ΔVWB/ΔT 15 ppm/°C Code = Mid-scale (80h or 40h) 5
Maximum current through A, W or B IW 2.5 mA Worst case current through wiper when wiper is Full Scale or Zero Scale (Note 6) 6
Leakage current into A, W or B IWL 100 nA MCP43X1 PxA = PxW = PxB = VSS 6
Full scale error (10k, 7-bit) VWFSE -2 -0.1 LSb 10 k 7-bit 3.0V ≤ VDD ≤ 5.5V 7
Zero scale error (10k, 7-bit) VWZSE 0.1 2 LSb 10 k 7-bit 3.0V ≤ VDD ≤ 5.5V 7
Potentiometer INL (7-bit) INL -0.5 0.25 0.5 LSb 7-bit, 3.0V ≤ VDD ≤ 5.5V, MCP43X1 only (Note 2); typ printed ±0.25 7
Potentiometer DNL (7-bit) DNL -0.25 0.125 0.25 LSb 7-bit, 3.0V ≤ VDD ≤ 5.5V, MCP43X1 only (Note 2); typ printed ±0.125 7
Bandwidth -3 dB (10k, 7-bit) BW 1 MHz 10 k 7-bit Code = 40h, load = 30 pF 7
Rheostat INL (10k, 7-bit, 5.5V) R-INL -1.125 0.5 1.125 LSb 10 k 7-bit 5.5V, IW = 450 µA; typ printed ±0.5 8
Rheostat INL (10k, 7-bit, 3.0V) R-INL -4 2.5 4 LSb 10 k 7-bit 3.0V, IW = 240 µA (Note 7) 8
Rheostat DNL (10k, 7-bit, 5.5V) R-DNL -0.375 0.25 0.375 LSb 10 k 7-bit 5.5V, IW = 450 µA; typ printed ±0.25 9
Rheostat DNL (10k, 7-bit, 3.0V) R-DNL -0.75 0.5 0.75 LSb 10 k 7-bit 3.0V, IW = 240 µA (Note 7) 9
Capacitance (PA) CAW 75 pF f =1 MHz, Code = Full Scale 10
Capacitance (PW) CW 120 pF f =1 MHz, Code = Full Scale 10
Capacitance (PB) CBW 75 pF f =1 MHz, Code = Full Scale 10
Schmitt trigger high input threshold VIH 0.45 V 2.7V ≤ VDD ≤ 5.5V, min printed 0.45 VDD 10
Schmitt trigger high input threshold (low VDD) VIH 0.5 V 1.8V ≤ VDD ≤ 2.7V, min printed 0.5 VDD 10
Schmitt trigger low input threshold VIL 0.2 V max printed 0.2 VDD 10
Hysteresis of Schmitt trigger inputs VHYS 0.1 V typ printed 0.1 VDD 10
High voltage input entry voltage VIHH 8.5 12.5 V (6) 10
High voltage limit VMAX 12.5 V Pin can tolerate VMAX or less 10
Output low voltage (SDO) VOL 0.3 V IOL = 5 mA, VDD = 5.5V; max printed 0.3 VDD 10
Output high voltage (SDO) VOH 0.7 V IOH = -2.5 mA, VDD = 5.5V; min printed 0.7 VDD 10
Weak pull-up current IPU 1.75 mA Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VCS = 12.5V 11
CS pull-up/pull-down resistance RCS 16 kΩ VDD = 5.5V, VCS = 3V 11
RESET pull-up resistance RRESET 16 kΩ VDD = 5.5V, VRESET = 0V 11
Input leakage current IIL -1 1 µA VIN = VDD (all pins) and VIN = VSS (all pins except RESET) 11
Pin capacitance CIN, COUT 10 pF fC = 20 MHz 11
Power supply sensitivity (7-bit) PSS 0.0015 0.0035 %/% 7-bit VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h 11
RESET pulse width tRST 50 ns 12
RESET rising edge to normal mode tRSTD 20 ns 12
SCK input frequency FSCK 10 MHz VDD = 2.7V to 5.5V 13
SCK input frequency FSCK 1 MHz VDD = 1.8V to 2.7V 13
SCK input high time TscH 45 ns VDD = 2.7V to 5.5V 13
SCK input low time TscL 45 ns VDD = 2.7V to 5.5V 13
SDO data output valid after SCK edge TscL2DOV 70 ns VDD = 2.7V to 5.5V 13
Voltage on VDD with respect to VSS VDD -0.6 7 V 3
Voltage on CS, SCK, SDI, RESET with respect to VSS -0.6 12.5 V 3
Maximum current into PxA, PxW and PxB pins -2.5 2.5 mA ±2.5 mA 3
Storage temperature -65 150 °C 3
Operating temperature range TA -40 125 °C 15
Thermal resistance, 20L-TSSOP θJA 90 °C/W 15

CAD (KiCad official)

  • Symbol: MCP4331-103E
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: mcp4331-103e-etched.step / mcp4331-103e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mcp4331-103e.step / mcp4331-103e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (88 pp, sha256 5666a7337dced900, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF