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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADF4002BCPZ-RL7

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-20(4x4)

ADF4002BCPZ-RL7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CPGND	power_in	Charge pump ground return path.
2	AGND	power_in	Analog ground return path for RF input stage.
3	AGND	power_in	Analog ground return path for RF input stage.
4	RFINB	input	Complementary RF input; must be decoupled to ground plane with 100 pF bypass capacitor.
5	RFINA	input	RF input signal ac-coupled to external VCO; frequency 5 to 400 MHz; input sensitivity −10 to 0 dBm.
6	AVDD	power_in	Analog power supply, 2.7 to 3.3 V; must equal DVDD.
7	AVDD	power_in	Analog power supply, 2.7 to 3.3 V; must equal DVDD.
8	REFIN	input	Reference clock input, CMOS with nominal threshold VDD/2; frequency 20 to 300 MHz; can be driven from TTL/CMOS crystal or ac-coupled.
9	DGND	power_in	Digital ground return path.
10	DGND	power_in	Digital ground return path.
11	CE	input	Chip enable input; logic low powers down device and puts charge pump into three-state mode.
12	CLK	input	Serial clock input; high impedance CMOS; data latched on rising edge at maximum rate 20 MHz.
13	DATA	input	Serial data input, high impedance CMOS; loaded MSB first with two LSBs as control bits.
14	LE	input	Load enable CMOS input; transfers data from shift registers to selected latch on high pulse; minimum pulse width 20 ns.
15	MUXOUT	output	Multiplexer output; selectable for lock detect, R counter, N counter, or internal signals via M3-M1 control bits.
16	DVDD	power_in	Digital power supply, 2.7 to 3.3 V; must equal AVDD.
17	DVDD	power_in	Digital power supply, 2.7 to 3.3 V; must equal AVDD.
18	VP	power_in	Charge pump power supply, AVDD to 5.5 V; allows VCO tuning range to 5 V in 3 V systems.
19	RSET	passive	External resistor to CPGND sets charge pump current per relationship ICP (mA) = 25.5 / RSET; range 3.0 to 11 kΩ; nominal voltage 0.66 V.
20	CP	output	Charge pump output; provides ±ICP (625 µA to 5 mA) to external loop filter when enabled; supports three-state mode.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-20(4x4)
Category	Clock/Timing
Pins	21

CAD (KiCad official)

Symbol: ADF4002BCPZ-RL7
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
3D model files: adf4002bcpz-rl7-etched.step / adf4002bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adf4002bcpz-rl7.step / adf4002bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (20 pp, sha256 fc5279ef463a7fa2, retrieved 2026-09-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF