STM32L071CBT6 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Digital power supply, 1.65 V to 3.6 V. Decouple with 100 nF close to the pin plus a bulk cap shared with the other VDD pins.
2	PC13	bidirectional	General-purpose I/O, FT-tolerant. Also RTC_TAMP1 / RTC_TS / RTC_OUT / WKUP2 wakeup input.
3	PC14/OSC32_IN	bidirectional	GPIO PC14; muxed with the 32 kHz LSE oscillator input OSC32_IN when the LSE is enabled in RCC.
4	PC15/OSC32_OUT	bidirectional	GPIO PC15; muxed with the 32 kHz LSE oscillator output OSC32_OUT when the LSE is enabled in RCC.
5	PH0/OSC_IN	bidirectional	GPIO PH0; muxed with the HSE crystal oscillator input OSC_IN when the HSE is enabled in RCC.
6	PH1/OSC_OUT	bidirectional	GPIO PH1; muxed with the HSE crystal oscillator output OSC_OUT when the HSE is enabled in RCC.
7	NRST	bidirectional	Bidirectional device reset input/open-drain output, active low. Pull up externally with ~10 kΩ; a 100 nF cap to VSS is recommended.
8	VSSA	power_in	Analog ground reference for VDDA and the ADC/comparators. Tie to the main ground plane, typically at a single star point.
9	VDDA	power_in	Analog supply for ADC, comparators, reset block, and PLL, 1.65 V to 3.6 V. Decouple with 100 nF + 1 μF close to the pin.
10	PA0	bidirectional	GPIO with TTa (5 V tolerant on this analog-adjacent pin). AF: TIM2_CH1, USART2_CTS, TIM2_ETR, USART4_TX, COMP1_OUT. Analog: COMP1_INM, ADC_IN0, RTC_TAMP2/WKUP1.
11	PA1	bidirectional	GPIO, FT. AF: EVENTOUT, TIM2_CH2, USART2_RTS/DE, TIM21_ETR, USART4_RX. Analog: COMP1_INP, ADC_IN1.
12	PA2	bidirectional	GPIO, FT. AF: TIM21_CH1, TIM2_CH3, USART2_TX, LPUART1_TX, COMP2_OUT. Analog: COMP2_INM, ADC_IN2.
13	PA3	bidirectional	GPIO, FT. AF: TIM21_CH2, TIM2_CH4, USART2_RX, LPUART1_RX. Analog: COMP2_INP, ADC_IN3.
14	PA4	bidirectional	GPIO, TC (3.3 V max, not 5 V tolerant). AF: SPI1_NSS, USART2_CK, TIM22_ETR. Analog: COMP1_INM, COMP2_INM, ADC_IN4.
15	PA5	bidirectional	GPIO, TC (3.3 V max, not 5 V tolerant). AF: SPI1_SCK, TIM2_ETR, TIM2_CH1. Analog: COMP1_INM, COMP2_INM, ADC_IN5.
16	PA6	bidirectional	GPIO, FT. AF: SPI1_MISO, TIM3_CH1, LPUART1_CTS, TIM22_CH1, EVENTOUT, COMP1_OUT. Analog: ADC_IN6.
17	PA7	bidirectional	GPIO, FT. AF: SPI1_MOSI, TIM3_CH2, TIM22_CH2, EVENTOUT, COMP2_OUT. Analog: ADC_IN7.
18	PB0	bidirectional	GPIO, FT. AF: EVENTOUT, TIM3_CH3. Analog: ADC_IN8, VREF_OUT.
19	PB1	bidirectional	GPIO, FT. AF: TIM3_CH4, LPUART1_RTS, LPUART1_DE. Analog: ADC_IN9, VREF_OUT.
20	PB2	bidirectional	GPIO, FT. AF: LPTIM1_OUT, I2C3_SMBA.
21	PB10	bidirectional	GPIO, FT. AF: TIM2_CH3, LPUART1_TX, SPI2_SCK, I2C2_SCL, LPUART1_RX.
22	PB11	bidirectional	GPIO, FT. AF: EVENTOUT, TIM2_CH4, LPUART1_RX, I2C2_SDA, LPUART1_TX.
23	VSS	power_in	Digital ground return. Bond to the main ground plane together with the other VSS pins.
24	VDDIO2	power_in	Independent I/O supply for the second I/O bank (drives certain PB/PC IOs), 1.65 V to 3.6 V. May be powered separately from VDD. Decouple with 100 nF close to the pin.
25	PB12	bidirectional	GPIO, FT. AF: SPI2_NSS/I2S2_WS, LPUART1_RTS/DE, I2C2_SMBA, EVENTOUT.
26	PB13	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: SPI2_SCK/I2S2_CK, MCO, LPUART1_CTS, I2C2_SCL, TIM21_CH1.
27	PB14	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: SPI2_MISO/I2S2_MCK, RTC_OUT, LPUART1_RTS/DE, I2C2_SDA, TIM21_CH2.
28	PB15	bidirectional	GPIO, FT. AF: SPI2_MOSI/I2S2_SD, RTC_REFIN.
29	PA8	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: MCO, EVENTOUT, USART1_CK, I2C3_SCL.
30	PA9	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: MCO, USART1_TX, I2C1_SCL, I2C3_SMBA.
31	PA10	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: USART1_RX, I2C1_SDA.
32	PA11	bidirectional	GPIO, FT. AF: SPI1_MISO, EVENTOUT, USART1_CTS, COMP1_OUT.
33	PA12	bidirectional	GPIO, FT. AF: SPI1_MOSI, EVENTOUT, USART1_RTS/DE, COMP2_OUT.
34	PA13	bidirectional	GPIO, FT. Default AF after reset: SWDIO (serial-wire debug data). AF: SWDIO, LPUART1_RX.
35	VSS	power_in	Digital ground return.
36	VDD	power_in	Digital power supply, 1.65 V to 3.6 V. Decouple with 100 nF close to the pin.
37	PA14	bidirectional	GPIO, FT. Default AF after reset: SWCLK (serial-wire debug clock). AF: SWCLK, USART2_TX, LPUART1_TX.
38	PA15	bidirectional	GPIO, FT. AF: SPI1_NSS, TIM2_ETR, EVENTOUT, USART2_RX, TIM2_CH1, USART4_RTS/DE.
39	PB3	bidirectional	GPIO, FT. AF: SPI1_SCK, TIM2_CH2, EVENTOUT, USART1_RTS/DE, USART5_TX. Analog: COMP2_INM.
40	PB4	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: SPI1_MISO, TIM3_CH1, TIM22_CH1, USART1_CTS, USART5_RX, I2C3_SDA. Analog: COMP2_INP.
41	PB5	bidirectional	GPIO, FT. AF: SPI1_MOSI, LPTIM1_IN1, I2C1_SMBA, TIM3_CH2/TIM22_CH2, USART1_CK, USART5_CK, USART5_RTS/DE. Analog: COMP2_INP.
42	PB6	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: USART1_TX, I2C1_SCL, LPTIM1_ETR. Analog: COMP2_INP.
43	PB7	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: USART1_RX, I2C1_SDA, LPTIM1_IN2, USART4_CTS. Analog: COMP2_INP, VREF_PVD_IN.
44	BOOT0	input	Boot mode selection input, latched at reset. Sampled together with the option-byte nBOOT1 to choose main Flash, system memory (ROM bootloader), or embedded SRAM as the boot region.
45	PB8	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: I2C1_SCL.
46	PB9	bidirectional	GPIO, FTf (5 V tolerant, I2C-Fm+ capable). AF: EVENTOUT, I2C1_SDA, SPI2_NSS/I2S2_WS.
47	VSS	power_in	Digital ground return.
48	VDD	power_in	Digital power supply, 1.65 V to 3.6 V. Decouple with 100 nF close to the pin.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	MCU
Pins	48

Ordering variants

Same part, different packaging or reel option.

STM32L071CBT6
STM32L071CBT6CBT7
STM32L071CBT6K8
STM32L071CBT6KB
STM32L071CBT6KZ
STM32L071CBT6K8U
STM32L071CBT6KBU
STM32L071CBT6KZU
STM32L071CBT6R8
STM32L071CBT6RB
STM32L071CBT6RZ
STM32L071CBT6R8H
STM32L071CBT6RBH
STM32L071CBT6RZH
STM32L071CBT6R8Y
STM32L071CBT6RBY
STM32L071CBT6RZY
STM32L071CBT6C8Y
STM32L071CBT6CBY
STM32L071CBT6CZY
STM32L071CBT6V8
STM32L071CBT6VB
STM32L071CBT6VZ
STM32L071CBT6V8H
STM32L071CBT6VBH
STM32L071CBT6VZH

CAD (KiCad official)

Symbol: STM32L071CBT6
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`stm32l071cbt6.step`	617 KB	You want the bare part, or you mark your own boards.
`stm32l071cbt6-etched.step`	4.5 MB	You want the part with `STM32L071CBT6` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 1143 faces against 747 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (144 pp, sha256 51e8b009862aa1de, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF