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MAX17205G+T
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Analog Devices Inc Maxim Integrated Battery Management, TDFN-14-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownMAX17205G+T
Analog Devices Inc Maxim Integrated · Battery Management · TDFN-14-EP(3x3)
MAX17205G+T from Analog Devices Inc Maxim Integrated, in a TDFN-14-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REG3 | power_out | Internal 3.4V regulator output that must be bypassed with an external 0.47µF capacitor on the MAX17205 (connect REG3 to VBATT on the MAX17201). |
| 2 | CSP | input | Current measurement positive sense point that must be Kelvin-connected to the cell side of the sense resistor. |
| 3 | REG2 | power_out | Internal 1.8V regulator output that must be bypassed with an external 0.47µF capacitor to CSN, with REG2 to CSN rated -0.3V to +2.2V. |
| 4 | CSN | power_in | Device ground and current measurement negative sense point that must be Kelvin-connected to the load side of the sense resistor. |
| 5 | VBATT | power_in | Power-supply and battery voltage sense input connected to the positive terminal of the cell stack, bypassed with an RC filter to CSN. |
| 6 | CELL2 | input | Voltage sense input for the second or middle cell, where its series resistance sets the balancing current and it also serves as the external divider gate drive for CELLx pack measurement. |
| 7 | CELL1 | input | Voltage sense input for the bottom cell, where its series resistance sets the balancing current. |
| 8 | ALRT1 | output | Programmable open-drain alert output that requires an external pullup to generate a logic-high, with a continuous sink current limit of 20mA. |
| 9 | AIN1 | input | Auxiliary voltage input 1 that receives the voltage from the external thermal-measurement network. |
| 10 | AIN2 | input | Auxiliary voltage input 2 that receives the voltage from the external thermal-measurement network. |
| 11 | OD/SCL | input | Input-only pin that serves as the I2C serial clock or the 1-Wire speed selection, with an internal pulldown used to sense pack disconnection. |
| 12 | DQ/SDA | bidirectional | Serial data input/output for both 1-Wire and I2C modes using an open-drain driver, with an internal pulldown used to sense pack disconnection and a continuous sink current limit of 20mA. |
| 13 | CELLx | input | High-impedance voltage measurement channel that connects to an external voltage divider for measuring cell stacks larger than 4S. |
| 14 | THRM | output | Thermistor bias connection to the high side of the thermistor divider, biased to the REG3 voltage during AIN1 and AIN2 measurement, with a continuous source current limit of 20mA. |
| 15 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | TDFN-14-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage VBATT (MAX17205/MAX17215) | VBATT | 4.2 | 20 | V | MAX17205/MAX17215 (Notes 1, 2) | 14 | |
| Shutdown Supply Current, multiple cell | IDD0 | 1.5 | 3 | μA | Multiple cell, shutdown mode (Note 3) | 14 | |
| Hibernate Supply Current, multiple cell | IDD1 | 12 | 25 | μA | Hibernate mode average current, multiple cell (Note 3) | 14 | |
| Active Supply Current, MAX17205/MAX17215 | IDD2 | 25 | 40 | μA | Not including thermistor measurement current (Note 3) | 14 | |
| Voltage Measurement Range, individual cell | VFS | 2.3 | 4.9 | V | Individual cell | 14 | |
| Voltage Measurement Range, VBATT pin | VBFS | 4.2 | 20 | V | VBATT pin | 14 | |
| Voltage Measurement Range, CELLx pin | VXFS | 0.92 | 2 | V | CELLx pin | 14 | |
| Voltage Measurement Error | VGERR | -12.5 | 12.5 | mV | TA = +25°C (Note 5) | 14 | |
| Voltage Measurement Error | VGERR | -25 | 25 | mV | (Note 5) | 14 | |
| Total VBATT Voltage Measurement Error | VBGERR | -30 | 30 | mV | TA = +25°C (Note 6) | 14 | |
| Total VBATT Voltage Measurement Error | VBGERR | -100 | 100 | mV | (Note 6) | 14 | |
| CELLx Voltage Measurement Error | VXGERR | -0.2 | 0.2 | % of reading | TA = +25°C (Note 7) | 14 | |
| CELLx Voltage Measurement Error | VXGERR | -0.5 | 0.5 | % of reading | (Note 7) | 14 | |
| Current Measurement Offset Error | IOERR | -2 | -0.7 | 0.5 | μV | VCSP = 0V, long-term average (Note 2) | 14 |
| Current Measurement Gain Error | IGERR | -1 | 1 | % of reading | CSP between -50mV and +50mV | 14 | |
| Current Measurement Range | IFS | -51.2 | 51.2 | mV | 15 | ||
| Internal Temperature Measurement Error | TIGERR | -1 | 1 | °C | 15 | ||
| Auxiliary Ratiometric Measurement Error | TEGERR | -0.5 | 0.5 | % of reading | 15 | ||
| Battery-Detach Detection Threshold | VDET | 91 | 95 | 99 | % | AIN1 as a fraction of the voltage of THRM, AIN1 rising (Note 1) | 15 |
| Output Drive Low, ALRT1, SDA/DQ | VOL | 0.4 | V | IOL = 4mA, VREG3 = 2.3V | 15 | ||
| Input Logic-High, SCL/OD, SDA/DQ | VIH | 1.5 | V | 15 | |||
| Input Logic-Low, SCL/OD, SDA/DQ | VIL | 0.44 | V | 15 | |||
| Overcurrent Threshold Offset Error | OCOE | -2.5 | 2.5 | mV | OD or SC comparator | 15 | |
| Overcurrent Threshold Gain Error | OCGE | -5 | 5 | % of threshold | OD or SC comparator | 15 | |
| Leakage Current, AIN1, AIN2 | ILEAK | -0.2 | 0.2 | μA | AIN1, AIN2 < REG3 | 15 | |
| Leakage Current, CELLx | ILEAK | -60 | 60 | nA | VCELLx < 2.0V (Note 2) | 15 | |
| Leakage Current, CELL1, CELL2, CSN, CSP, ALRT1, THRM | ILEAK | -1 | 1 | μA | VALRT1 < 15V, THRM < REG3 | 16 | |
| Cell-Balancing Resistance | RBAL | 3 | 9 | 20 | Ω | VBATT = 12.6V, IBAL = 50mA, between VBATT-CELL2, CELL2-CELL1, and CELL1-CSN (TDFN) or CELL1-GND (WLP) | 16 |
| Input Pulldown Current | IPD | 0.05 | 0.2 | 0.4 | μA | VSDA, VSCL pins = 0.4V | 16 |
| Time-Base Accuracy | tERR | -1 | 1 | % | TA= +25°C | 16 | |
| SHA Calculation Time | tSHA | 4.5 | 10 | ms | 16 | ||
| Programming Supply Current | IPROG | 4 | 10 | mA | Current from VBATT for block programming | 16 | |
| Block Programming Time | tBLOCK | 368 | 7360 | ms | 16 | ||
| Page Programming Time | tUPDATE | 64 | 1280 | ms | SHA secret update or learned parameters update | 16 | |
| SCL Clock Frequency | fSCL | 0 | 400 | kHz | (Note 10) | 17 | |
| Data Hold Time | tHD:DAT | 0 | 0.9 | µs | (Notes 12, 13) | 17 | |
| Rise Time of Both SDA and SCL Signals | tR | 5 | 300 | ns | 17 | ||
| Fall Time of Both SDA and SCL Signals | tF | 5 | 300 | ns | 18 | ||
| VBATT to CSN (MAX17205/MAX17215) | VBATT | -0.3 | 22 | V | 13 | ||
| ALRT1 to CSN | ALRT1 | -0.3 | 17 | V | 13 | ||
| REG3 to CSN (MAX17205/MAX17215) | REG3 | -0.3 | 6 | V | 13 | ||
| AIN1, AIN2 to CSN | AIN1, AIN2 | -0.3 | 6 | V | 13 | ||
| REG2 to CSN | REG2 | -0.3 | 2.2 | V | 13 | ||
| CSP to CSN | CSP | -2 | 2 | V | 13 | ||
| DQ/SDA, OD/SCL to CSN | DQ/SDA, OD/SCL | -0.3 | 6 | V | 13 | ||
| Continuous Source Current for THRM | 20 | mA | 13 | ||||
| Continuous Sink Current for DQ/SDA, ALRT1 | 20 | mA | 13 | ||||
| Continuous Sink Current for BATT, CELL1, CELL2 | 50 | mA | 13 | ||||
| Operating Temperature Range | TA | -40 | 85 | °C | 13 | ||
| Storage Temperature Range | -55 | 125 | °C | 13 | |||
| Lead Temperature (soldering 10s) | 300 | °C | soldering 10s | 13 | |||
| Soldering Temperature (reflow) | 260 | °C | 13 | ||||
| Thermal Resistance, Single Layer Board, Junction-to-Ambient (θJA) | θJA | 54 | °C/W | TDFN, single layer board | 13 | ||
| Thermal Resistance, Single Layer Board, Junction-to-Case (θJC) | θJC | 8 | °C/W | TDFN, single layer board | 13 | ||
| Thermal Resistance, Four Layer Board, Junction-to-Ambient (θJA) | θJA | 41 | °C/W | TDFN, four layer board | 13 | ||
| Thermal Resistance, Four Layer Board, Junction-to-Case (θJC) | θJC | 8 | °C/W | TDFN, four layer board | 13 |
CAD (KiCad official)
- Symbol:
MAX17205G+T - Footprint:
Package_DFN_QFN:DFN-14-1EP_3x3mm_P0.4mm_EP1.78x2.35mm - 3D model: TDFN-14-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
max17205g-t-etched.step/max17205g-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);max17205g-t.step/max17205g-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc Maxim Integrated datasheet (115 pp, sha256
7a77e041ceb5fd46, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).