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GD32F450VET6

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GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersgd32f450vet6factory-2.0.0extractor-text
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Contents

README

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GD32F450VET6

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

GD32F450VET6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional Default GPIO PE2, 5 V tolerant (5VT); alternates include TRACECLK, SPI3_SCK, ETH_MII_TXD3, EXMC_A23 and EVENTOUT.
2 PE3 bidirectional Default GPIO PE3, 5 V tolerant (5VT); alternates include TRACED0, EXMC_A19 and EVENTOUT.
3 PE4 bidirectional Default GPIO PE4, 5 V tolerant (5VT); alternates include TRACED1, SPI3_NSS, EXMC_A20, DCI_D4, TLI_B0 and EVENTOUT.
4 PE5 bidirectional Default GPIO PE5, 5 V tolerant (5VT); alternates include TRACED2, TIMER8_CH0, SPI3_MISO, EXMC_A21, DCI_D6, TLI_G0 and EVENTOUT.
5 PE6 bidirectional Default GPIO PE6, 5 V tolerant (5VT); alternates include TRACED3, TIMER8_CH1, SPI3_MOSI, EXMC_A22, DCI_D7, TLI_G1 and EVENTOUT.
6 VBAT power_in Default function VBAT; the block diagram labels the backup-domain blocks as powered by VBAT.
7 PC13-TAMPER-RTC bidirectional Default GPIO PC13, 5 V tolerant (5VT); additional functions RTC_TAMP0, RTC_OUT and RTC_TS, plus EVENTOUT.
8 PC14-OSC32_IN bidirectional Default GPIO PC14, 5 V tolerant (5VT); additional function OSC32IN, the low-speed oscillator input.
9 PC15-OSC32_OUT bidirectional Default GPIO PC15, 5 V tolerant (5VT); additional function OSC32OUT, the low-speed oscillator output.
10 VSS power_in Ground pin (default VSS).
11 VDD power_in Digital supply pin (default VDD).
12 PH0-OSC_IN bidirectional Default GPIO PH0, 5 V tolerant (5VT); additional function OSCIN, the high-speed crystal input (4-32 MHz HXTAL per the clock tree).
13 PH1-OSC_OUT bidirectional Default GPIO PH1, 5 V tolerant (5VT); additional function OSCOUT, the high-speed crystal output.
14 NRST input Reset pin (default NRST); the pin definitions table gives no further electrical limits for it.
15 PC0 bidirectional Default GPIO PC0, 5 V tolerant (5VT); alternates include USBHS_ULPI_STP, EXMC_SDNWE and EVENTOUT; additional ADC012_IN10.
16 PC1 bidirectional Default GPIO PC1, 5 V tolerant (5VT); alternates include SPI2_MOSI/I2S2_SD, SPI1_MOSI/I2S1_SD, ETH_MDC and EVENTOUT; additional ADC012_IN11.
17 PC2 bidirectional Default GPIO PC2, 5 V tolerant (5VT); alternates include SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, ETH_MII_TXD2 and EXMC_SDNE0; additional ADC012_IN12.
18 PC3 bidirectional Default GPIO PC3, 5 V tolerant (5VT); alternates include SPI1_MOSI/I2S1_SD, USBHS_ULPI_NXT, ETH_MII_TX_CLK and EXMC_SDCKE0; additional ADC012_IN13.
19 VDD power_in Digital supply pin (default VDD).
20 VSSA power_in Analog ground pin (default VSSA).
21 VREF+ power_in Positive voltage reference pin (default VREF+).
22 VDDA power_in Analog supply pin (default VDDA).
23 PA0-WKUP bidirectional Default GPIO PA0, 5 V tolerant (5VT); additional ADC012_IN0 and WKUP function; alternates include TIMER1_CH0, TIMER4_CH0, USART1_CTS, UART3_TX and ETH_MII_CRS.
24 PA1 bidirectional Default GPIO PA1, 5 V tolerant (5VT); additional ADC012_IN1; alternates include TIMER1_CH1, TIMER4_CH1, SPI3_MOSI, USART1_RTS, UART3_RX and ETH_MII_RX_CLK/ETH_RMII_REF_CLK.
25 PA2 bidirectional Default GPIO PA2, 5 V tolerant (5VT); additional ADC012_IN2; alternates include TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX and ETH_MDIO.
26 PA3 bidirectional Default GPIO PA3, 5 V tolerant (5VT); additional ADC012_IN3; alternates include TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0 and TLI_B5.
27 VSS power_in Ground pin (default VSS).
28 VDD power_in Digital supply pin (default VDD).
29 PA4 bidirectional Default GPIO PA4, level listed as TTa (not 5VT); additional ADC01_IN4 and DAC_OUT0; alternates include SPI0_NSS, SPI2_NSS/I2S2_WS, USART1_CK, USBHS_SOF and TLI_VSYNC.
30 PA5 bidirectional Default GPIO PA5, level listed as TTa (not 5VT); additional ADC01_IN5 and DAC_OUT1; alternates include TIMER1_CH0/TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK and USBHS_ULPI_CK.
31 PA6 bidirectional Default GPIO PA6, 5 V tolerant (5VT); additional ADC01_IN6; alternates include TIMER0_BRKIN, TIMER2_CH0, SPI0_MISO, I2S1_MCK, SDIO_CMD, DCI_PIXCLK and TLI_G2.
32 PA7 bidirectional Default GPIO PA7, 5 V tolerant (5VT); additional ADC01_IN7; alternates include TIMER0_CH0_ON, TIMER2_CH1, SPI0_MOSI, ETH_MII_RX_DV/ETH_RMII_CRS_DV and EXMC_SDNWE.
33 PC4 bidirectional Default GPIO PC4, 5 V tolerant (5VT); additional ADC01_IN14; alternates include ETH_MII_RXD0/ETH_RMII_RXD0 and EXMC_SDNE0.
34 PC5 bidirectional Default GPIO PC5, 5 V tolerant (5VT); additional ADC01_IN15; alternates include USART2_RX, ETH_MII_RXD1/ETH_RMII_RXD1 and EXMC_SDCKE0.
35 PB0 bidirectional Default GPIO PB0, 5 V tolerant (5VT); additional ADC01_IN8 and IREF; alternates include TIMER0_CH1_ON, TIMER2_CH2, SPI4_SCK, SPI2_MOSI/I2S2_SD, TLI_R3, USBHS_ULPI_D1 and SDIO_D1.
36 PB1 bidirectional Default GPIO PB1, 5 V tolerant (5VT); additional ADC01_IN9; alternates include TIMER0_CH2_ON, TIMER2_CH3, SPI4_NSS, TLI_R6, USBHS_ULPI_D2 and SDIO_D2.
37 PB2 bidirectional Default GPIO PB2 with BOOT1 function, 5 V tolerant (5VT); alternates include TIMER1_CH3, SPI2_MOSI/I2S2_SD, USBHS_ULPI_D4 and SDIO_CK.
38 PE7 bidirectional Default GPIO PE7, 5 V tolerant (5VT); alternates include TIMER0_ETI, UART6_RX, EXMC_D4 and EVENTOUT.
39 PE8 bidirectional Default GPIO PE8, 5 V tolerant (5VT); alternates include TIMER0_CH0_ON, UART6_TX and EXMC_D5.
40 PE9 bidirectional Default GPIO PE9, 5 V tolerant (5VT); alternates include TIMER0_CH0 and EXMC_D6.
41 PE10 bidirectional Default GPIO PE10, 5 V tolerant (5VT); alternates include TIMER0_CH1_ON and EXMC_D7.
42 PE11 bidirectional Default GPIO PE11, 5 V tolerant (5VT); alternates include TIMER0_CH1, SPI3_NSS, SPI4_NSS, EXMC_D8 and TLI_G3.
43 PE12 bidirectional Default GPIO PE12, 5 V tolerant (5VT); alternates include TIMER0_CH2_ON, SPI3_SCK, SPI4_SCK, EXMC_D9 and TLI_B4.
44 PE13 bidirectional Default GPIO PE13, 5 V tolerant (5VT); alternates include TIMER0_CH2, SPI3_MISO, SPI4_MISO, EXMC_D10 and TLI_DE.
45 PE14 bidirectional Default GPIO PE14, 5 V tolerant (5VT); alternates include TIMER0_CH3, SPI3_MOSI, SPI4_MOSI, EXMC_D11 and TLI_PIXCLK.
46 PE15 bidirectional Default GPIO PE15, 5 V tolerant (5VT); alternates include TIMER0_BRKIN, EXMC_D12 and TLI_R7.
47 PB10 bidirectional Default GPIO PB10, 5 V tolerant (5VT); alternates include TIMER1_CH2, I2C1_SCL, SPI1_SCK/I2S1_CK, USART2_TX, USBHS_ULPI_D3, ETH_MII_RX_ER and SDIO_D7.
48 PB11 bidirectional Default GPIO PB11, 5 V tolerant (5VT); alternates include TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4 and ETH_MII_TX_EN/ETH_RMII_TX_EN.
49 NC unconnected Listed as NC in the pin name column with default function VCORE and type P; no further limits are given in the excerpt.
50 VDD power_in Digital supply pin (default VDD).
51 PB12 bidirectional Default GPIO PB12, 5 V tolerant (5VT); alternates include TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS/I2S1_WS, SPI3_NSS, USART2_CK, CAN1_RX, USBHS_ULPI_D5 and USBHS_ID.
52 PB13 bidirectional Default GPIO PB13, 5 V tolerant (5VT); additional USBHS_VBUS; alternates include TIMER0_CH0_ON, SPI1_SCK/I2S1_CK, SPI3_SCK, USART2_CTS, CAN1_TX and USBHS_ULPI_D6.
53 PB14 bidirectional Default GPIO PB14, 5 V tolerant (5VT); alternates include TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0 and USBHS_DM.
54 PB15 bidirectional Default GPIO PB15, 5 V tolerant (5VT); alternates include RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI/I2S1_SD, TIMER11_CH1 and USBHS_DP.
55 PD8 bidirectional Default GPIO PD8, 5 V tolerant (5VT); alternates include USART2_TX and EXMC_D13.
56 PD9 bidirectional Default GPIO PD9, 5 V tolerant (5VT); alternates include USART2_RX and EXMC_D14.
57 PD10 bidirectional Default GPIO PD10, 5 V tolerant (5VT); alternates include USART2_CK, EXMC_D15 and TLI_B3.
58 PD11 bidirectional Default GPIO PD11, 5 V tolerant (5VT); alternates include USART2_CTS and EXMC_A16.
59 PD12 bidirectional Default GPIO PD12, 5 V tolerant (5VT); alternates include TIMER3_CH0, USART2_RTS and EXMC_A17.
60 PD13 bidirectional Default GPIO PD13, 5 V tolerant (5VT); alternates include TIMER3_CH1 and EXMC_A18.
61 PD14 bidirectional Default GPIO PD14, 5 V tolerant (5VT); alternates include TIMER3_CH2 and EXMC_D0.
62 PD15 bidirectional Default GPIO PD15, 5 V tolerant (5VT); alternates include CTC_SYNC, TIMER3_CH3 and EXMC_D1.
63 PC6 bidirectional Default GPIO PC6, 5 V tolerant (5VT); alternates include TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0 and TLI_HSYNC.
64 PC7 bidirectional Default GPIO PC7, 5 V tolerant (5VT); alternates include TIMER2_CH1, TIMER7_CH1, SPI1_SCK/I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1 and TLI_G6.
65 PC8 bidirectional Default GPIO PC8, 5 V tolerant (5VT); alternates include TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0 and DCI_D2.
66 PC9 bidirectional Default GPIO PC9, 5 V tolerant (5VT); alternates include CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1 and DCI_D3.
67 PA8 bidirectional Default GPIO PA8, 5 V tolerant (5VT); alternates include CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, CTC_SYNC, USBFS_SOF, SDIO_D1 and TLI_R6.
68 PA9 bidirectional Default GPIO PA9, 5 V tolerant (5VT); additional USBFS_VBUS; alternates include TIMER0_CH1, I2C2_SMBA, SPI1_SCK/I2S1_CK, USART0_TX, SDIO_D2 and DCI_D0.
69 PA10 bidirectional Default GPIO PA10, 5 V tolerant (5VT); alternates include TIMER0_CH2, I2C2_TXFRAME, SPI4_MOSI, USART0_RX, USBFS_ID and DCI_D1.
70 PA11 bidirectional Default GPIO PA11, 5 V tolerant (5VT); alternates include TIMER0_CH3, SPI3_MISO, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM and TLI_R4.
71 PA12 bidirectional Default GPIO PA12, 5 V tolerant (5VT); alternates include TIMER0_ETI, SPI4_MISO, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP and TLI_R5.
72 PA13 bidirectional Default function JTMS/SWDIO and PA13, 5 V tolerant (5VT); alternate function EVENTOUT.
73 NC unconnected Listed as NC in the pin definitions table with no function assigned.
74 VSS power_in Ground pin (default VSS).
75 VDD power_in Digital supply pin (default VDD).
76 PA14 bidirectional Default function JTCK/SWCLK and PA14, 5 V tolerant (5VT); alternate function EVENTOUT.
77 PA15 bidirectional Default function JTDI and PA15, 5 V tolerant (5VT); alternates include TIMER1_CH0/TIMER1_ETI, SPI0_NSS, SPI2_NSS/I2S2_WS and USART0_TX.
78 PC10 bidirectional Default GPIO PC10, 5 V tolerant (5VT); alternates include SPI2_SCK/I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8 and TLI_R2.
79 PC11 bidirectional Default GPIO PC11, 5 V tolerant (5VT); alternates include I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3 and DCI_D4.
80 PC12 bidirectional Default GPIO PC12, 5 V tolerant (5VT); alternates include I2C1_SDA, SPI2_MOSI/I2S2_SD, USART2_CK, UART4_TX, SDIO_CK and DCI_D9.
81 PD0 bidirectional Default GPIO PD0, 5 V tolerant (5VT); alternates include SPI3_MISO, SPI2_MOSI/I2S2_SD, CAN0_RX and EXMC_D2.
82 PD1 bidirectional Default GPIO PD1, 5 V tolerant (5VT); alternates include SPI1_NSS/I2S1_WS, CAN0_TX and EXMC_D3.
83 PD2 bidirectional Default GPIO PD2, 5 V tolerant (5VT); alternates include TIMER2_ETI, UART4_RX, SDIO_CMD and DCI_D11.
84 PD3 bidirectional Default GPIO PD3, 5 V tolerant (5VT); alternates include TRACED1, SPI1_SCK/I2S1_CK, USART1_CTS, EXMC_CLK, DCI_D5 and TLI_G7.
85 PD4 bidirectional Default GPIO PD4, 5 V tolerant (5VT); alternates include USART1_RTS and EXMC_NOE.
86 PD5 bidirectional Default GPIO PD5, 5 V tolerant (5VT); alternates include USART1_TX and EXMC_NWE.
87 PD6 bidirectional Default GPIO PD6, 5 V tolerant (5VT); alternates include SPI2_MOSI/I2S2_SD, USART1_RX, EXMC_NWAIT, DCI_D10 and TLI_B2.
88 PD7 bidirectional Default GPIO PD7, 5 V tolerant (5VT); alternates include USART1_CK and EXMC_NE0/EXMC_NCE1.
89 PB3 bidirectional Default function JTDO/TRACESWO and PB3, 5 V tolerant (5VT); alternates include TIMER1_CH1, SPI0_SCK, SPI2_SCK/I2S2_CK, USART0_RX and I2C1_SDA.
90 PB4 bidirectional Default function JNTRST and PB4, 5 V tolerant (5VT); alternates include TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA and SDIO_D0.
91 PB5 bidirectional Default GPIO PB5, 5 V tolerant (5VT); alternates include TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI/I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ETH_PPS_OUT and EXMC_SDCKE1.
92 PB6 bidirectional Default GPIO PB6, 5 V tolerant (5VT); alternates include TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, EXMC_SDNE1 and DCI_D5.
93 PB7 bidirectional Default GPIO PB7, 5 V tolerant (5VT); alternates include TIMER3_CH1, I2C0_SDA, USART0_RX, EXMC_NL and DCI_VSYNC.
94 BOOT0 bidirectional Default function BOOT0, 5 V tolerant (5VT), listed as an I/O pin in the pin definitions table.
95 PB8 bidirectional Default GPIO PB8, 5 V tolerant (5VT); alternates include TIMER1_CH0/TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, SPI4_MOSI, CAN0_RX, ETH_MII_TXD3 and SDIO_D4.
96 PB9 bidirectional Default GPIO PB9, 5 V tolerant (5VT); alternates include TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS/I2S1_WS, CAN0_TX, SDIO_D5 and DCI_D7.
97 PE0 bidirectional Default GPIO PE0, 5 V tolerant (5VT); alternates include TIMER3_ETI, UART7_RX, EXMC_NBL0 and DCI_D2.
98 PE1 bidirectional Default GPIO PE1, 5 V tolerant (5VT); alternates include TIMER0_CH1_ON, UART7_TX, EXMC_NBL1 and DCI_D3.
99 VSS power_in Ground pin (default VSS).
100 VDD power_in Digital supply pin (default VDD).

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External voltage range (VDD) VDD 3.6 V 49
External analog supply voltage (VDDA) VDDA 3.6 V 49
External battery supply voltage (VBAT) VBAT 3.6 V 49
Input voltage on other I/O VIN 4 V 49
Maximum current for GPIO pins IIO 25 mA 49
Operating temperature range TA -40 85 °C 49
Storage temperature range TSTG -55 150 °C 49
Maximum junction temperature TJ 125 °C 49
Supply voltage VDD 2.6 3.3 3.6 V 49
Analog supply voltage VDDA 2.6 3.3 3.6 V Same as VDD 49
Battery supply voltage VBAT 1.8 3.6 V 49
Power on reset threshold VPOR 2.3 2.4 2.48 V 52
Power down reset threshold VPDR 1.72 1.8 1.88 V 52
Electrostatic discharge voltage (human body model) VESD(HBM) 7000 V TA=25 °C; JESD22-A114 52
Electrostatic discharge voltage (charge device model) VESD(CDM) 800 V TA=25 °C; JESD22-C101 52
Static latch-up I-test LU (I-test) -200 200 mA TA=25 °C; JESD78 52
Static latch-up supply over voltage 5.4 V 52
High Speed External oscillator (HXTAL) frequency fHXTAL 4 8 32 MHz VDD=5.0V 53
Recommended load capacitance on OSC_IN and OSC_OUT CHXTAL 20 30 pF 53
HXTAL oscillator duty cycle DHXTAL 30 50 70 % 53
Recommended load capacitance on OSC32_IN and OSC32_OUT CLXTAL 15 pF 53
LXTAL oscillator duty cycle DLXTAL 30 50 70 % 53
IRC16M oscillator Frequency accuracy, Factory-trimmed ACCIRC16M -4 5 % VDD=3.3V, TA=-40°C ~+105°C 54
IRC16M oscillator Frequency accuracy, Factory-trimmed ACCIRC16M -2 2 % VDD=3.3V, TA=0°C ~ +85°C 54
IRC16M oscillator Frequency accuracy, Factory-trimmed ACCIRC16M -1 1 % VDD=3.3V, TA=25°C 54
IRC16M oscillator duty cycle DIRC16M 45 50 55 % VDD=3.3V, fIRC16M=16MHz 54
IRC16M oscillator operating current IDDIRC16M 66 80 μA VDD=3.3V, fIRC16M=16MHz 54
IRC48M oscillator Frequency accuracy, Factory-trimmed ACCIRC48M -4 5 % VDD=3.3V, TA=-40°C ~+105°C 54
IRC48M oscillator Frequency accuracy, Factory-trimmed ACCIRC48M -3 3 % VDD=3.3V, TA=0°C ~ +85°C 54
IRC48M oscillator Frequency accuracy, Factory-trimmed ACCIRC48M -2 2 % VDD=3.3V, TA=25°C 54
IRC48M oscillator duty cycle DIRC48M 45 50 55 % VDD=3.3V, fIRC48M=16MHz 54
IRC48M oscillator operating current IDDIRC48M 240 300 μA VDD=3.3V, fIRC48M=16MHz 54
Low Speed Internal oscillator (IRC32K) frequency fIRC32K 20 32 45 KHz VDD=VBAT=3.3V, TA=-40°C ~ +85°C 55
IRC32K oscillator operating current IDDIRC32K 0.4 0.6 μA VDD=VBAT=3.3V, TA=25°C 55
PLL input clock frequency fPLLIN 1 4 MHz 55
PLL output clock frequency fPLL 100 500 MHz 55
Modulation frequency (SSCG) FMOD 10 KHz 55
Peak modulation amplitude (SSCG) Mdamp 2 % 55
Number of guaranteed program/erase cycles before failure (Endurance) PECYC 100 kcycles TA=-40°C ~ +85°C 56
Data retention time tRET 20 years TA=125°C 56
Word programming time tPROG 200 400 us TA=-40°C ~ +85°C 56
Page erase time tERASE 60 100 450 ms TA=-40°C ~ +85°C 56
Mass erase time tMERASE 3.2 9.6 s TA=-40°C ~ +85°C 56
Standard IO Low level input voltage VIL 1.27 V VDD=2.6V 57
Standard IO Low level input voltage VIL 1.58 V VDD=3.3V 57
Standard IO Low level input voltage VIL 1.71 V VDD=3.6V 57
Standard IO High level input voltage VIH 1.4 V VDD=2.6V 57
Standard IO High level input voltage VIH 1.71 V VDD=3.3V 57
Standard IO High level input voltage VIH 1.84 V VDD=3.6V 57
Low level output voltage VOL 0.17 V VDD=2.6V, IIO=8mA 57
Low level output voltage VOL 0.16 V VDD=3.3V, IIO=8mA 57
High level output voltage VOH 2.39 V VDD=2.6V, IIO=8mA 57
High level output voltage VOH 3.12 V VDD=3.3V, IIO=8mA 57
High level output voltage VOH 3.41 V VDD=3.6V, IIO=8mA 57
Internal pull-up resistor RPU 30 40 50 kΩ VIN=VSS 57
Internal pull-down resistor RPD 30 40 50 kΩ VIN=VDD 57
ADC clock fADC 0.1 40 MHz 58
External input impedance RAIN 52.1 kΩ See Equation 2 58
Sampling time ts 0.075 12 μs fADC=40MHz 58

CAD (KiCad official)

  • Symbol: GD32F450VET6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: gd32f450vet6-etched.step / gd32f450vet6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f450vet6.step / gd32f450vet6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (66 pp, sha256 915c24a1f84de32a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF