component
STM32L151RBT6TR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSTM32L151RBT6TR
STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
STM32L151RBT6TR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VLCD | power_in | LCD power supply pin; note 3 states that for STM32L151xx devices this pin should be connected to VDD. |
| 2 | PC13-WKUP2 | bidirectional | 5 V tolerant (FT) general-purpose I/O PC13, also RTC_TAMP1, RTC_TS, RTC_OUT and WKUP2 wakeup function. |
| 3 | PC14-OSC32_IN | bidirectional | Standard 3.3 V (TC) I/O PC14, used as OSC32_IN only when the LSE oscillator is on (LSEON in RCC_CSR), otherwise usable as GPIO with LSE having priority. |
| 4 | PC15-OSC32_OUT | bidirectional | Standard 3.3 V (TC) I/O PC15, used as OSC32_OUT only when the LSE oscillator is on (LSEON in RCC_CSR), otherwise usable as GPIO with LSE having priority. |
| 5 | PH0-OSC_IN | bidirectional | Standard 3.3 V (TC) I/O PH0, used as OSC_IN only when the HSE oscillator is on (HSEON in RCC_CR), otherwise usable as GPIO with HSE having priority. |
| 6 | PH1-OSC_OUT | bidirectional | Standard 3.3 V (TC) I/O PH1, used as OSC_OUT only when the HSE oscillator is on (HSEON in RCC_CR), otherwise usable as GPIO with HSE having priority. |
| 7 | NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up resistor. |
| 8 | PC0 | bidirectional | 5 V tolerant (FT) I/O PC0 with analog inputs ADC_IN10 and COMP1_INP and alternate function LCD_SEG18 as printed. |
| 9 | PC1 | bidirectional | 5 V tolerant (FT) I/O PC1 with analog inputs ADC_IN11 and COMP1_INP and alternate function LCD_SEG19 as printed. |
| 10 | PC2 | bidirectional | 5 V tolerant (FT) I/O PC2 with analog inputs ADC_IN12 and COMP1_INP and alternate function LCD_SEG20 as printed. |
| 11 | PC3 | bidirectional | Standard 3.3 V (TC) I/O PC3 with analog inputs ADC_IN13 and COMP1_INP and alternate function LCD_SEG21 as printed. |
| 12 | VSSA | power_in | Analog ground pin; VSSA must be tied to ground. |
| 13 | VDDA | power_in | Analog supply pin; ADC characteristics specify VDDA from 1.8 V to 3.6 V. |
| 14 | PA0-WKUP1 | bidirectional | 5 V tolerant (FT) I/O PA0 with USART2_CTS and TIM2_CH1_ETR alternate functions, plus WKUP1, ADC_IN0 and COMP1_INP. |
| 15 | PA1 | bidirectional | 5 V tolerant (FT) I/O PA1 with USART2_RTS, TIM2_CH2 and LCD_SEG0 alternate functions, plus ADC_IN1 and COMP1_INP. |
| 16 | PA2 | bidirectional | 5 V tolerant (FT) I/O PA2 with USART2_TX, TIM2_CH3, TIM9_CH1 and LCD_SEG1 alternate functions, plus ADC_IN2 and COMP1_INP. |
| 17 | PA3 | bidirectional | Standard 3.3 V (TC) I/O PA3 with USART2_RX, TIM2_CH4, TIM9_CH2 and LCD_SEG2 alternate functions, plus ADC_IN3 and COMP1_INP. |
| 18 | VSS_4 | power_in | Digital ground pin. |
| 19 | VDD_4 | power_in | Digital supply pin; for this ordering option (no T option character) the VDD range is 1.8 V to 3.6 V with BOR enabled. |
| 20 | PA4 | bidirectional | Standard 3.3 V (TC) I/O PA4 with SPI1_NSS and USART2_CK alternate functions, plus ADC_IN4, DAC_OUT1 and COMP1_INP. |
| 21 | PA5 | bidirectional | Standard 3.3 V (TC) I/O PA5 with SPI1_SCK and TIM2_CH1_ETR alternate functions, plus ADC_IN5, DAC_OUT2 and COMP1_INP. |
| 22 | PA6 | bidirectional | 5 V tolerant (FT) I/O PA6 with SPI1_MISO, TIM3_CH1, LCD_SEG3 and TIM10_CH1 alternate functions, plus ADC_IN6 and COMP1_INP. |
| 23 | PA7 | bidirectional | 5 V tolerant (FT) I/O PA7 with SPI1_MOSI, TIM3_CH2, LCD_SEG4 and TIM11_CH1 alternate functions, plus ADC_IN7 and COMP1_INP. |
| 24 | PC4 | bidirectional | 5 V tolerant (FT) I/O PC4 with alternate function LCD_SEG22 as printed, plus ADC_IN14 and COMP1_INP. |
| 25 | PC5 | bidirectional | 5 V tolerant (FT) I/O PC5 with alternate function LCD_SEG23 as printed, plus ADC_IN15 and COMP1_INP. |
| 26 | PB0 | bidirectional | Standard 3.3 V (TC) I/O PB0 with TIM3_CH3 and LCD_SEG5 alternate functions, plus ADC_IN8, COMP1_INP and VREF_OUT. |
| 27 | PB1 | bidirectional | 5 V tolerant (FT) I/O PB1 with TIM3_CH4 and LCD_SEG6 alternate functions, plus ADC_IN9, COMP1_INP and VREF_OUT. |
| 28 | PB2/BOOT1 | bidirectional | 5 V tolerant (FT) I/O PB2 that is also the BOOT1 boot-mode pin. |
| 29 | PB10 | bidirectional | 5 V tolerant (FT) I/O PB10 with I2C2_SCL, USART3_TX, TIM2_CH3 and LCD_SEG10 alternate functions. |
| 30 | PB11 | bidirectional | 5 V tolerant (FT) I/O PB11 with I2C2_SDA, USART3_RX, TIM2_CH4 and LCD_SEG11 alternate functions. |
| 31 | VSS_1 | power_in | Digital ground pin. |
| 32 | VDD_1 | power_in | Digital supply pin; for this ordering option the VDD range is 1.8 V to 3.6 V with BOR enabled. |
| 33 | PB12 | bidirectional | 5 V tolerant (FT) I/O PB12 with SPI2_NSS, I2C2_SMBA, USART3_CK, LCD_SEG12 and TIM10_CH1 alternate functions, plus ADC_IN18 and COMP1_INP. |
| 34 | PB13 | bidirectional | 5 V tolerant (FT) I/O PB13 with SPI2_SCK, USART3_CTS, LCD_SEG13 and TIM9_CH1 alternate functions, plus ADC_IN19 and COMP1_INP. |
| 35 | PB14 | bidirectional | 5 V tolerant (FT) I/O PB14 with SPI2_MISO, USART3_RTS, LCD_SEG14 and TIM9_CH2 alternate functions, plus ADC_IN20 and COMP1_INP. |
| 36 | PB15 | bidirectional | 5 V tolerant (FT) I/O PB15 with SPI2_MOSI, LCD_SEG15 and TIM11_CH1 alternate functions, plus ADC_IN21, COMP1_INP and RTC_REFIN. |
| 37 | PC6 | bidirectional | 5 V tolerant (FT) I/O PC6 with TIM3_CH1 and LCD_SEG24 alternate functions. |
| 38 | PC7 | bidirectional | 5 V tolerant (FT) I/O PC7 with TIM3_CH2 and LCD_SEG25 alternate functions. |
| 39 | PC8 | bidirectional | 5 V tolerant (FT) I/O PC8 with TIM3_CH3 and LCD_SEG26 alternate functions. |
| 40 | PC9 | bidirectional | 5 V tolerant (FT) I/O PC9 with TIM3_CH4 and LCD_SEG27 alternate functions. |
| 41 | PA8 | bidirectional | 5 V tolerant (FT) I/O PA8 with USART1_CK, MCO and LCD_COM0 alternate functions. |
| 42 | PA9 | bidirectional | 5 V tolerant (FT) I/O PA9 with USART1_TX and LCD_COM1 alternate functions. |
| 43 | PA10 | bidirectional | 5 V tolerant (FT) I/O PA10 with USART1_RX and LCD_COM2 alternate functions. |
| 44 | PA11 | bidirectional | 5 V tolerant (FT) I/O PA11 with USART1_CTS and SPI1_MISO alternate functions, and USB_DM as additional function. |
| 45 | PA12 | bidirectional | 5 V tolerant (FT) I/O PA12 with USART1_RTS and SPI1_MOSI alternate functions, and USB_DP as additional function. |
| 46 | PA13 | bidirectional | 5 V tolerant (FT) I/O PA13 with JTMS-SWDIO debug function. |
| 47 | VSS_2 | power_in | Digital ground pin. |
| 48 | VDD_2 | power_in | Digital supply pin; for this ordering option the VDD range is 1.8 V to 3.6 V with BOR enabled. |
| 49 | PA14 | bidirectional | 5 V tolerant (FT) I/O PA14 with JTCK-SWCLK debug function. |
| 50 | PA15 | bidirectional | 5 V tolerant (FT) I/O PA15 with JTDI, TIM2_CH1_ETR, SPI1_NSS and LCD_SEG17 alternate functions. |
| 51 | PC10 | bidirectional | 5 V tolerant (FT) I/O PC10 with USART3_TX, LCD_SEG28, LCD_SEG40 and LCD_COM4 alternate functions as printed. |
| 52 | PC11 | bidirectional | 5 V tolerant (FT) I/O PC11 with USART3_RX, LCD_SEG29, LCD_SEG41 and LCD_COM5 alternate functions as printed. |
| 53 | PC12 | bidirectional | 5 V tolerant (FT) I/O PC12 with USART3_CK, LCD_SEG30, LCD_SEG42 and LCD_COM6 alternate functions as printed. |
| 54 | PD2 | bidirectional | 5 V tolerant (FT) I/O PD2 with TIM3_ETR, LCD_SEG31, LCD_SEG43 and LCD_COM7 alternate functions as printed. |
| 55 | PB3 | bidirectional | 5 V tolerant (FT) I/O PB3 with JTDO, TIM2_CH2, SPI1_SCK and LCD_SEG7 alternate functions, plus COMP2_INM. |
| 56 | PB4 | bidirectional | 5 V tolerant (FT) I/O PB4 with NJTRST, TIM3_CH1, SPI1_MISO and LCD_SEG8 alternate functions, plus COMP2_INP. |
| 57 | PB5 | bidirectional | 5 V tolerant (FT) I/O PB5 with I2C1_SMBA, TIM3_CH2, SPI1_MOSI and LCD_SEG9 alternate functions, plus COMP2_INP. |
| 58 | PB6 | bidirectional | 5 V tolerant (FT) I/O PB6 with I2C1_SCL, TIM4_CH1 and USART1_TX alternate functions. |
| 59 | PB7 | bidirectional | 5 V tolerant (FT) I/O PB7 with I2C1_SDA, TIM4_CH2 and USART1_RX alternate functions, and PVD_IN as additional function. |
| 60 | BOOT0 | input | Dedicated BOOT0 boot-mode selection pin (input only, dedicated structure). |
| 61 | PB8 | bidirectional | 5 V tolerant (FT) I/O PB8 with TIM4_CH3, I2C1_SCL, LCD_SEG16 and TIM10_CH1 alternate functions. |
| 62 | PB9 | bidirectional | 5 V tolerant (FT) I/O PB9 with TIM4_CH4, I2C1_SDA, LCD_COM3 and TIM11_CH1 alternate functions. |
| 63 | VSS_3 | power_in | Digital ground pin. |
| 64 | VDD_3 | power_in | Digital supply pin; for this ordering option the VDD range is 1.8 V to 3.6 V with BOR enabled. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
STM32L151RBT6TR - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
stm32l151rbt6tr-etched.step/stm32l151rbt6tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stm32l151rbt6tr.step/stm32l151rbt6tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (133 pp, sha256
5223296de36fe904, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).