component
MSP430FR5870IRGCR
Public Made by Adomby adom
Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMSP430FR5870IRGCR
Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-64-EP(9x9)
MSP430FR5870IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P4.3/UCA0SOMI/UCA0RXD/UCB1STE | bidirectional | General-purpose I/O P4.3 (reset default OFF, high-impedance after BOR) with eUSCI_A0 SOMI/RXD and eUSCI_B1 STE alternate functions, powered from DVCC. |
| 2 | P1.4/UCB0CLK/UCA0STE/TA1.0 | bidirectional | General-purpose I/O P1.4 (reset default OFF) with eUSCI_B0 clock, eUSCI_A0 STE and Timer_A1 CCR0 alternate functions, powered from DVCC. |
| 3 | P1.5/UCB0STE/UCA0CLK/TA0.0 | bidirectional | General-purpose I/O P1.5 (reset default OFF) with eUSCI_B0 STE, eUSCI_A0 clock and Timer_A0 CCR0 alternate functions, powered from DVCC. |
| 4 | P1.6/UCB0SIMO/UCB0SDA/TA0.1 | bidirectional | General-purpose I/O P1.6 (reset default OFF) with eUSCI_B0 SIMO/SDA, I2C BSL data and Timer_A0 CCR1 alternate functions, powered from DVCC. |
| 5 | P1.7/UCB0SOMI/UCB0SCL/TA0.2 | bidirectional | General-purpose I/O P1.7 (reset default OFF) with eUSCI_B0 SOMI/SCL, I2C BSL clock and Timer_A0 CCR2 alternate functions, powered from DVCC. |
| 6 | DNC | unconnected | Do not connect; TI strongly recommends leaving this pin not connected. |
| 7 | P6.0 | bidirectional | General-purpose digital I/O P6.0 (reset default OFF), powered from DVCC. |
| 8 | P6.1 | bidirectional | General-purpose digital I/O P6.1 (reset default OFF), powered from DVCC. |
| 9 | P6.2/COUT | bidirectional | General-purpose digital I/O P6.2 (reset default OFF) with comparator output COUT alternate function, powered from DVCC. |
| 10 | P6.3 | bidirectional | General-purpose digital I/O P6.3 (reset default OFF), powered from DVCC. |
| 11 | P6.4/TB0.0 | bidirectional | General-purpose digital I/O P6.4 (reset default OFF) with Timer_B0 CCR0 alternate function, powered from DVCC. |
| 12 | P6.5/TB0.1 | bidirectional | General-purpose digital I/O P6.5 (reset default OFF) with Timer_B0 CCR1 alternate function, powered from DVCC. |
| 13 | P6.6/TB0.2 | bidirectional | General-purpose digital I/O P6.6 (reset default OFF) with Timer_B0 CCR2 alternate function, powered from DVCC. |
| 14 | P3.0/UCB1CLK/TA3.2 | bidirectional | General-purpose I/O P3.0 (reset default OFF) with eUSCI_B1 clock and Timer_A3 CCR2 alternate functions, powered from DVCC. |
| 15 | P3.1/UCB1SIMO/UCB1SDA/TA3.3 | bidirectional | General-purpose I/O P3.1 (reset default OFF) with eUSCI_B1 SIMO/SDA and Timer_A3 CCR3 alternate functions, powered from DVCC. |
| 16 | P3.2/UCB1SOMI/UCB1SCL/TA3.4 | bidirectional | General-purpose I/O P3.2 (reset default OFF) with eUSCI_B1 SOMI/SCL and Timer_A3 CCR4 alternate functions, powered from DVCC. |
| 17 | DVSS1 | power_in | Digital ground supply (VSS, 0 V reference for all voltages). |
| 18 | DVCC1 | power_in | Digital power supply; VCC 1.8 V to 3.6 V at all DVCC and AVCC pins, with a 1 µF plus 100 nF low-ESR decoupling per pin pair. |
| 19 | TEST/SBWTCK | input | Test mode pin selecting digital I/O on JTAG pins, with internal pulldown always enabled; also Spy-Bi-Wire input clock SBWTCK. |
| 20 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (external reset pulse at least 2 µs), with alternate functions nonmaskable interrupt NMI and Spy-Bi-Wire data SBWTDIO. |
| 21 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 | bidirectional | JTAG pin PJ.0 (TDO) that can be used as general-purpose I/O when JTAG is not used, with TB0OUTH, SMCLK and SRSCG1 alternate functions. |
| 22 | PJ.1/TDI/TCLK/MCLK/SRSCG0 | bidirectional | JTAG pin PJ.1 (TDI/TCLK) that can be used as general-purpose I/O when JTAG is not used, with MCLK and SRSCG0 alternate functions. |
| 23 | PJ.2/TMS/ACLK/SROSCOFF | bidirectional | JTAG pin PJ.2 (TMS) that can be used as general-purpose I/O when JTAG is not used, with ACLK and SROSCOFF alternate functions. |
| 24 | PJ.3/TCK/COUT/SRCPUOFF | bidirectional | JTAG pin PJ.3 (TCK) that can be used as general-purpose I/O when JTAG is not used, with COUT and SRCPUOFF alternate functions. |
| 25 | P3.3/TA1.1/TB0CLK | bidirectional | General-purpose I/O P3.3 (reset default OFF) with Timer_A1 CCR1 and Timer_B0 clock TB0CLK alternate functions, powered from DVCC. |
| 26 | P3.4/UCA1SIMO/UCA1TXD/TB0.0 | bidirectional | General-purpose I/O P3.4 (reset default OFF) with eUSCI_A1 SIMO/TXD and Timer_B0 CCR0 alternate functions, powered from DVCC. |
| 27 | P3.5/UCA1SOMI/UCA1RXD/TB0.1 | bidirectional | General-purpose I/O P3.5 (reset default OFF) with eUSCI_A1 SOMI/RXD and Timer_B0 CCR1 alternate functions, powered from DVCC. |
| 28 | P3.6/UCA1CLK/TB0.2 | bidirectional | General-purpose I/O P3.6 (reset default OFF) with eUSCI_A1 clock and Timer_B0 CCR2 alternate functions, powered from DVCC. |
| 29 | P3.7/UCA1STE/TB0.3 | bidirectional | General-purpose I/O P3.7 (reset default OFF) with eUSCI_A1 STE and Timer_B0 CCR3 alternate functions, powered from DVCC. |
| 30 | P2.3/UCA0STE/TB0OUTH | bidirectional | General-purpose I/O P2.3 (reset default OFF) with eUSCI_A0 STE and TB0OUTH alternate functions, powered from DVCC. |
| 31 | P2.2/UCA0CLK/TB0.4/RTCCLK | bidirectional | General-purpose I/O P2.2 (reset default OFF) with eUSCI_A0 clock, Timer_B0 CCR4 and RTC clock output RTCCLK alternate functions, powered from DVCC. |
| 32 | P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0 | bidirectional | General-purpose I/O P2.1 (reset default OFF) with eUSCI_A0 SOMI/RXD, UART BSL receive, Timer_B0 CCR5 and DMA external trigger DMAE0 alternate functions, powered from DVCC. |
| 33 | P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK | bidirectional | General-purpose I/O P2.0 (reset default OFF) with eUSCI_A0 SIMO/TXD, UART BSL transmit, Timer_B0 CCR6 and TB0CLK alternate functions, powered from DVCC. |
| 34 | P7.0/TA0CLK | bidirectional | General-purpose I/O P7.0 (reset default OFF) with Timer_A0 clock input TA0CLK alternate function, powered from DVCC. |
| 35 | P7.1/TA0.0/ACLK | bidirectional | General-purpose I/O P7.1 (reset default OFF) with Timer_A0 CCR0 and ACLK output alternate functions, powered from DVCC. |
| 36 | P7.2/TA0.1 | bidirectional | General-purpose I/O P7.2 (reset default OFF) with Timer_A0 CCR1 alternate function, powered from DVCC. |
| 37 | P7.3/TA0.2 | bidirectional | General-purpose I/O P7.3 (reset default OFF) with Timer_A0 CCR2 alternate function, powered from DVCC. |
| 38 | P7.4/SMCLK | bidirectional | General-purpose I/O P7.4 (reset default OFF) with SMCLK output alternate function, powered from DVCC. |
| 39 | DVSS2 | power_in | Digital ground supply (VSS, 0 V reference for all voltages). |
| 40 | DVCC2 | power_in | Digital power supply; VCC 1.8 V to 3.6 V at all DVCC and AVCC pins, with a 1 µF plus 100 nF low-ESR decoupling per pin pair. |
| 41 | P1.3/TA1.2/A3/C3 | bidirectional | General-purpose I/O P1.3 (reset default OFF) with Timer_A1 CCR2, ADC analog input A3 and comparator input C3 alternate functions. |
| 42 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | General-purpose I/O P1.2 (reset default OFF) with Timer_A1 CCR1, TA0CLK, comparator output COUT, ADC analog input A2 and comparator input C2 alternate functions. |
| 43 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | General-purpose I/O P1.1 (reset default OFF) with Timer_A0 CCR2, TA1CLK, COUT, ADC analog input A1, comparator input C1, positive reference output VREF+ and external positive reference input VeREF+ alternate functions. |
| 44 | P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- | bidirectional | General-purpose I/O P1.0 (reset default OFF) with Timer_A0 CCR1, DMA trigger DMAE0, RTCCLK, ADC analog input A0, comparator input C0, negative reference output VREF- and external negative reference input VeREF- alternate functions. |
| 45 | P9.4/A12/C12 | bidirectional | General-purpose I/O P9.4 (reset default OFF) with ADC analog input A12 and comparator input C12 alternate functions. |
| 46 | P9.5/A13/C13 | bidirectional | General-purpose I/O P9.5 (reset default OFF) with ADC analog input A13 and comparator input C13 alternate functions. |
| 47 | P9.6/A14/C14 | bidirectional | General-purpose I/O P9.6 (reset default OFF) with ADC analog input A14 and comparator input C14 alternate functions. |
| 48 | P9.7/A15/C15 | bidirectional | General-purpose I/O P9.7 (reset default OFF) with ADC analog input A15 and comparator input C15 alternate functions. |
| 49 | AVCC1 | power_in | Analog power supply; VCC 1.8 V to 3.6 V, TI recommends powering AVCC and DVCC from the same source and keeping their difference within the absolute maximum limit of ±0.3 V. |
| 50 | AVSS1 | power_in | Analog ground supply (VSS, 0 V reference). |
| 51 | PJ.4/LFXIN | input | Port PJ.4 that serves as the input terminal of the 32-kHz crystal oscillator LFXT (LFXIN), also usable as bypass clock input when LFXTBYPASS is set. |
| 52 | PJ.5/LFXOUT | output | Port PJ.5 that serves as the output terminal of the 32-kHz crystal oscillator LFXT (LFXOUT); can be used as general-purpose I/O when LFXT bypass mode is selected. |
| 53 | AVSS2 | power_in | Analog ground supply (VSS, 0 V reference). |
| 54 | PJ.7/HFXOUT | output | Port PJ.7 that serves as the output terminal of the high-frequency crystal oscillator HFXT (HFXOUT); can be used as general-purpose I/O when HFXT bypass mode is selected. |
| 55 | PJ.6/HFXIN | input | Port PJ.6 that serves as the input terminal of the high-frequency crystal oscillator HFXT (HFXIN), also usable as bypass clock input when HFXTBYPASS is set. |
| 56 | AVSS3 | power_in | Analog ground supply (VSS, 0 V reference). |
| 57 | P5.7/UCA1STE/TB0CLK | bidirectional | General-purpose I/O P5.7 (reset default OFF) with eUSCI_A1 STE and Timer_B0 clock TB0CLK alternate functions, powered from DVCC. |
| 58 | P4.4/UCB1STE/TA1CLK | bidirectional | General-purpose I/O P4.4 (reset default OFF) with eUSCI_B1 STE and Timer_A1 clock TA1CLK alternate functions, powered from DVCC. |
| 59 | P4.5/UCB1CLK/TA1.0 | bidirectional | General-purpose I/O P4.5 (reset default OFF) with eUSCI_B1 clock and Timer_A1 CCR0 alternate functions, powered from DVCC. |
| 60 | P4.6/UCB1SIMO/UCB1SDA/TA1.1 | bidirectional | General-purpose I/O P4.6 (reset default OFF) with eUSCI_B1 SIMO/SDA and Timer_A1 CCR1 alternate functions, powered from DVCC. |
| 61 | P4.7/UCB1SOMI/UCB1SCL/TA1.2 | bidirectional | General-purpose I/O P4.7 (reset default OFF) with eUSCI_B1 SOMI/SCL and Timer_A1 CCR2 alternate functions, powered from DVCC. |
| 62 | DVSS3 | power_in | Digital ground supply (VSS, 0 V reference for all voltages). |
| 63 | DVCC3 | power_in | Digital power supply; VCC 1.8 V to 3.6 V at all DVCC and AVCC pins, with a 1 µF plus 100 nF low-ESR decoupling per pin pair. |
| 64 | P4.2/UCA0SIMO/UCA0TXD/UCB1CLK | bidirectional | General-purpose I/O P4.2 (reset default OFF) with eUSCI_A0 SIMO/TXD and eUSCI_B1 clock alternate functions, powered from DVCC. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 65 |
CAD (KiCad official)
- Symbol:
MSP430FR5870IRGCR - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
msp430fr5870irgcr-etched.step/msp430fr5870irgcr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr5870irgcr.step/msp430fr5870irgcr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (149 pp, sha256
9c7ec644ff1873e2, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).