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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

GL3523-ONY30

Genesys Logic · USB ICs · QFN-48-EP(6x6)

GL3523-ONY30 from Genesys Logic, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDD12	power_in	Analog 1.2V power input for the analog PLL circuit.
2	AVDD33_2	power_in	Analog 3.3V power input.
3	DP_P3	bidirectional	USB 2.0 D+ for downstream port 3 (DSPORT3).
4	DM_P3	bidirectional	USB 2.0 D- for downstream port 3 (DSPORT3).
5	TXN1_P3	output	USB 3.1 Gen 1 differential data transmitter TX- of DSPORT3.
6	TXP1_P3	output	USB 3.1 Gen 1 differential data transmitter TX+ of DSPORT3.
7	VP12_P3	power_in	Analog 1.2V power input for the analog circuit (port 3).
8	RXN1_P3	input	USB 3.1 Gen 1 differential data receiver RX- of DSPORT3.
9	RXP1_P3	input	USB 3.1 Gen 1 differential data receiver RX+ of DSPORT3.
10	TXN1_P2	output	USB 3.1 Gen 1 differential data transmitter TX- of DSPORT2.
11	TXP1_P2	output	USB 3.1 Gen 1 differential data transmitter TX+ of DSPORT2.
12	VP12_P2	power_in	Analog 1.2V power input for the analog circuit (port 2).
13	RXN1_P2	input	USB 3.1 Gen 1 differential data receiver RX- of DSPORT2.
14	RXP1_P2	input	USB 3.1 Gen 1 differential data receiver RX+ of DSPORT2.
15	DP_P2	bidirectional	USB 2.0 D+ for downstream port 2 (DSPORT2).
16	DM_P2	bidirectional	USB 2.0 D- for downstream port 2 (DSPORT2).
17	AVDD33_3	power_in	Analog 3.3V power input.
18	PWREN3J	output	Active-low power enable output for DSPORT3.
19	OVCUR3J	input	Active-low over-current indicator input for DSPORT3, with internal pull-down.
20	OVCUR2J	input	Active-low over-current indicator input for DSPORT2, with internal pull-down.
21	PWREN2J	output	Active-low power enable output for DSPORT2.
22	FB	passive	Switching regulator feedback input (inverting input of error amplifier); for the fixed-voltage version connect to the output voltage.
23	VSSP	power_in	Dedicated ground for the embedded switching regulator.
24	SW	passive	Internal switch output of the 5V-to-1.2V regulator; connect to the output inductor.
25	VDDP	power_in	Dedicated 5V power input for the embedded switching regulator.
26	V5	power_in	5V power input; connect to V33 if using an external 3.3V regulator.
27	V33	power_in	5V-to-3.3V regulator output and 3.3V input.
28	RTERM	passive	A 20 kohm resistor must be connected between RTERM and ground.
29	DVDD12	power_in	1.2V digital power input for digital circuits.
30	RESETJ	input	Active-low external reset input with internal pull-down, default pulled high with 10 kohm; low resets the whole chip.
31	P_SPI_DO	bidirectional	SPI data pin (listed as SPI data input).
32	P_SPI_CK	bidirectional	SPI data clock.
33	P_SPI_DI	bidirectional	SPI data pin (listed as SPI data output).
34	P_SPI_CZ	bidirectional	SPI data chip enable.
35	PGANG	input	Input after power-on reset; individual/gang mode is strapped during this period.
36	VBUS	power_in	VBUS detection pin for valid VBUS.
37	DVDD33	power_in	3.3V digital power input for digital circuits.
38	X2	output	Crystal clock output (25 MHz crystal).
39	X1	input	Crystal / oscillator clock input (25 MHz).
40	AVDD33_1	power_in	Analog 3.3V power input.
41	DP_P0	bidirectional	USB 2.0 D+ for the upstream port (USPORT).
42	DM_P0	bidirectional	USB 2.0 D- for the upstream port (USPORT).
43	TXN1_P0	output	USB 3.1 Gen 1 differential data transmitter TX- of USPORT.
44	TXP1_P0	output	USB 3.1 Gen 1 differential data transmitter TX+ of USPORT.
45	VP12_P0	power_in	Analog 1.2V power input for the analog circuit (upstream port).
46	RXN1_P0	input	USB 3.1 Gen 1 differential data receiver RX- of USPORT.
47	RXP1_P0	input	USB 3.1 Gen 1 differential data receiver RX+ of USPORT.
48	AVDD33	power_in	Analog 3.3V power input.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Genesys Logic
Package	QFN-48-EP(6x6)
Category	Interface ICs
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
5V Power Supply	V5	-0.5		6	V		37
3.3V Power Supply	VDD	-0.5		3.6	V		37
1.2V Power Supply	VDDcore	-0.5		1.32	V		37
3.3V Input Voltage for digital I/O (EE_DO) pins	VIN	-0.5		5	V		37
1.2V input voltage	Vincore	-0.5		1.32	V		37
Input Voltage for USB signal (DP, DM) pins	VINUSB	-0.5		3.6	V		37
Storage Temperature under bias	TS	-60		100	oC		37
Frequency tolerance	FOSC	-0.03		0.03	%	25 MHz	37
5V Power Supply	V5	4.75	5	5.25	V		37
3.3V Power Supply	VDD	3	3.3	3.6	V		37
1.2V Power Supply	VDDcore	1.15	1.2	1.32	V		37
Input Voltage for digital I/O pins	VIND	-0.5	3.3	3.6	V		37
Input Voltage for USB signal (DP, DM) pins	VINUSB	0.5	3.3	3.6	V		37
Ambient Temperature	TA	0		70	oC		37
Absolute maximum junction temperature	TJ	0		125	oC		37
Power Supply Voltage	VDD	3	3.3	3.6	V		38
LOW level input voltage	VIL			1	V		38
HIGH level input voltage	VIH	1.4			V		38
Schmitt trigger PAD LOW to HIGH threshold voltage	VTLH	1.7			V	Schmitt trigger pads are VBUS, RESET	38
Schmitt trigger PAD HIGH to LOW threshold voltage	VTHL			0.7	V	Schmitt trigger pads are VBUS, RESET	38
LOW level output voltage	VOL			0.4	V	IOL=8mA	38
HIGH level output voltage	VOH	2.4			V	IOH=8mA	38
Leakage current for pads with internal pull up or pull down resistor	IOLK			30	A		38
Pad internal pull down resister	RDN	232	378	647	KΩ		38
Pad internal pull up resister	RUP	276	435	718	KΩ		38
External clock frequency tolerance		-300		300	ppm	25MHz external 3.3V clock source at XIN	41
5V to 3.3V regulator maximum quiescent current			80	125	uA		40

CAD (KiCad official)

Symbol: GL3523-ONY30
Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
3D model: QFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: gl3523-ony30-etched.step / gl3523-ony30-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gl3523-ony30.step / gl3523-ony30.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Genesys Logic datasheet (47 pp, sha256 49c6b9f4d38fe1a7, retrieved 2026-10-26, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF