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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

BQ25883RGET

Texas Instruments · Battery Management · VQFN-24-EP(4x4)

BQ25883RGET from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D-	bidirectional	Negative USB data line used for D+/D- based USB host/charging port detection, including data contact detection and BC1.2 secondary detection.
2	STAT	output	Open-drain charge status indicator that must be pulled up to the rail through 10 kΩ, reads LOW during charge in progress, and blinks at 1 Hz on any fault; the absolute maximum output sink current is 6 mA.
3	CE	input	Active-low charge enable input where charging is enabled only when EN_CHG is 1 and CE is LOW, with an internal 900 kΩ pull-down; the absolute maximum voltage is 6 V.
4	SDA	bidirectional	I2C serial data line, open-drain, to be connected to the pull-up rail through 10 kΩ, with an absolute maximum voltage of 6 V.
5	SCL	input	I2C serial clock line, open-drain, to be connected to the pull-up rail through 10 kΩ, with an absolute maximum voltage of 6 V.
6	INT	output	Open-drain active-low interrupt output, pulled up through 10 kΩ, that sends a 256 µs pulse to the host to report charger status and faults.
7	TS	input	Temperature qualification input for an NTC thermistor (103AT-2 recommended), with the temperature window set by a resistor divider from REGN to TS to GND and charging suspended when TS is out of range; the absolute maximum voltage is 6 V.
8	ILIM	input	Input current limit pin that regulates at 0.8 V to set the maximum input current (IINDPM), can monitor input current, must not be left floating and should be tied to GND if unused, and input current limits below 500 mA are not supported on this pin.
9	PG	output	Open-drain active-low power good indicator, pulled up through 10 kΩ, that goes LOW when VBUS is within VVBUS_OP (3.9 V) and the source can supply more than IPOORSRC (30 mA).
10	NC	unconnected	No connect pin that should be left floating or tied to ground.
11	REGN	power_out	Gate-drive and internal bias supply output from the REGN LDO, which must be bypassed to GND with a 4.7 µF ceramic capacitor and has a 50 mA current limit.
12	BTST	passive	High-side driver bootstrap supply, internally connected to the bootstrap diode cathode, requiring a 47 nF bootstrap capacitor connected from SW to BTST.
13	BAT	passive	Battery power connection that requires a minimum of 10 µF capacitance, derated and placed closely between BAT and GND.
14	BAT	passive	Battery power connection that requires a minimum of 10 µF capacitance, derated and placed closely between BAT and GND.
15	SYS	passive	System connection to which the internal BATFET is connected between SYS and BAT, requiring 2x22 µF of derated capacitance placed closely to SYS and PGND.
16	SYS	passive	System connection to which the internal BATFET is connected between SYS and BAT, requiring 2x22 µF of derated capacitance placed closely to SYS and PGND.
17	SW	passive	Inductor connection to the switched side of the external inductor; the absolute maximum voltage is 13 V.
18	SW	passive	Inductor connection to the switched side of the external inductor; the absolute maximum voltage is 13 V.
19	GND	power_in	Ground return pin.
20	GND	power_in	Ground return pin.
21	PMID	passive	Blocking MOSFET connection, where the total input low-ESR capacitance on VBUS and PMID must be at least 10 µF after derating (at least 1 µF at VBUS, with the remainder typically 10 µF at PMID).
22	PMID	passive	Blocking MOSFET connection, where the total input low-ESR capacitance on VBUS and PMID must be at least 10 µF after derating (at least 1 µF at VBUS, with the remainder typically 10 µF at PMID).
23	VBUS	power_in	Input supply connected to the external DC supply, requiring at least 1 µF ceramic bypass to GND placed as close to the IC as possible; the absolute maximum voltage is 20 V.
24	D+	bidirectional	Positive USB data line used for D+/D- based USB host/charging port detection, including data contact detection and BC1.2 secondary detection.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	Power Management (PMIC)
Pins	25

CAD (KiCad official)

Symbol: BQ25883RGET
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: bq25883rget-etched.step / bq25883rget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq25883rget.step / bq25883rget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (86 pp, sha256 9d1c382c59a15d39, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF