component
NCV8184PDR2G
Public Unreviewedby Ray
onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCV8184PDR2G
onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP
NCV8184PDR2G from onsemi, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Regulated buffered output. Tracks VREF/ENABLE within ±3.0 mV over 2.1 V ≤ VREF ≤ (VIN − 600 mV); sources up to 70 mA (guaranteed) with typical 0.35 V dropout at 50 mA. Requires an output capacitor (COUT typ. 1.0 µF, ESR ≈ 1.0 Ω). |
| 2 | NC | unconnected | No connection on the SOIC-8 EP (PD suffix) variant. PCB traces are allowed under this pin. |
| 3 | GND | power_in | Device ground. On the SOIC-8 EP variant, pin 3 and the exposed pad both connect to GND and should be tied together on the PCB. |
| 4 | Adj | input | Adjust (feedback) input; noninverting input of the internal error amplifier. Typical input bias current 0.2 µA (max 6.0 µA at VREF = 5.0 V). Tie to VOUT for unity-gain buffer operation, or drive from a resistive divider to scale the tracked reference. |
| 5 | VREF/ENABLE | input | Reference-voltage input and ENABLE. VOUT tracks the voltage on this pin over 2.1 V ≤ VREF/ENABLE ≤ (VIN − 600 mV). Enable threshold is 0.8-2.1 V; pulling below ~0.8 V shuts the regulator down (quiescent current drops to ≈20 µA). Typical input bias current 0.2 µA (max 3.0 µA). Absolute max −0.3 to 45 V. |
| 6 | NC | unconnected | No connection on the SOIC-8 EP (PD suffix) variant. PCB traces are allowed under this pin. |
| 7 | NC | unconnected | No connection on the SOIC-8 EP (PD suffix) variant. PCB traces are allowed under this pin. |
| 8 | VIN | power_in | Battery / supply input. Recommended operating range 4.0-42 V; absolute-max supply −15 to +45 V continuous, tolerates 45 V load-dump transient. Quiescent current typ. 5 mA at IOUT = 60 mA (7 mA max). |
| 9 | GND | power_in | Exposed thermal pad on the underside of the SOIC-8 EP package. Electrically connected to GND (must be tied to pin 3 / system ground) and used to conduct heat into the PCB copper for reduced RθJA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
NCV8184PDR2GPDGNCV8184PDR2GNCV8184PDR2GDGNCV8184PDR2GDTRKG
CAD (KiCad official)
- Symbol:
NCV8184PDR2G - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (None pp, sha256
a92ed07058078fc3, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).