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LT1366CN8#PBF

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Analog Devices Operational Amplifier, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentoperational amplifier-comparatorlt1366cn8#pbffactory-2.0.0extractor-text

Verified LT1366CN8#PBF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LT1366CN8#PBF · PDIP-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C663522, digikey LT1366CN8#PBF-ND, mouser 584-LT1366CN8#PBF
  • ✓family: DIP-8_W7.62mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-jviojjui/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lt1366cn8-pbf.kicad_sym✓ lt1366cn8-pbf.kicad_mod✓ lt1366cn8-pbf.step
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Contents

README

markdown

LT1366CN8#PBF

Analog Devices · Operational Amplifier · PDIP-8

LT1366CN8#PBF from Analog Devices, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT A output Output of amplifier A, which swings rail-to-rail and can source or sink up to 30mA per the datasheet's high output drive specification.
2 -IN A input Inverting input of amplifier A; the input common mode range includes both supply rails.
3 +IN A input Non-inverting input of amplifier A; the input common mode range includes both supply rails.
4 V- power_in Negative supply rail; the device operates over a total supply range of 1.8V to 36V (V+ to V-).
5 +IN B input Non-inverting input of amplifier B; the input common mode range includes both supply rails.
6 -IN B input Inverting input of amplifier B; the input common mode range includes both supply rails.
7 OUT B output Output of amplifier B, which swings rail-to-rail and can source or sink up to 30mA per the datasheet's high output drive specification.
8 V+ power_in Positive supply rail; the device operates over a total supply range of 1.8V to 36V (V+ to V-).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package PDIP-8
Category Operational Amplifier/Comparator
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Total Supply Voltage 36 V V+ to V- 2
Input Current -15 15 mA 2
Operating Temperature Range -40 85 °C 2
Storage Temperature Range -65 150 °C 2
Junction Temperature TJMAX 150 °C 2
Lead Temperature (Soldering, 10 sec) 300 °C 2
Specified Temperature Range 0 70 °C 2
Input Offset Voltage (LT1366/LT1368) VCM=VCC VOS 150 475 µV TA = 25°C; VS = 5V, 0V; VCM = VCC 3
Input Offset Voltage (LT1366/LT1368) VCM=VEE VOS 150 475 µV TA = 25°C; VS = 5V, 0V; VCM = VEE 3
Input Offset Voltage Shift (LT1366/LT1368) ∆VOS 150 400 µV TA = 25°C; VS = 5V, 0V; VCM = VEE to VCC 3
Input Offset Voltage Match (Channel to Channel) ∆VOS 250 700 µV TA = 25°C; VS = 5V, 0V; VCM = VEE, VCC (Notes 4, 5) 3
Input Bias Current VCM=VCC IB 0 10 35 nA TA = 25°C; VS = 5V, 0V; VCM = VCC 3
Input Bias Current VCM=VEE IB -35 -10 0 nA TA = 25°C; VS = 5V, 0V; VCM = VEE 3
Input Bias Current Shift ∆IB 20 70 nA TA = 25°C; VS = 5V, 0V; VCM = VEE to VCC 3
Input Offset Current VCM=VCC IOS 1 12 nA TA = 25°C; VS = 5V, 0V; VCM = VCC 3
Input Offset Current VCM=VEE IOS 0.3 12 nA TA = 25°C; VS = 5V, 0V; VCM = VEE 3
Input Offset Current Shift ∆IOS 1 12 nA TA = 25°C; VS = 5V, 0V; VCM = VEE to VCC 3
Large-Signal Voltage Gain AVOL 250 2000 V/mV TA = 25°C; VS = 5V, 0V; VO = 50mV to 4.8V, RL = 10k 3
Common Mode Rejection Ratio (LT1366/LT1368) CMRR 81 90 dB TA = 25°C; VS = 5V, 0V; VCM = VEE to VCC 3
CMRR Match (Channel to Channel) CMRR 75 90 dB TA = 25°C; VS = 5V, 0V; VCM = VEE to VCC (Note 4) 3
Power Supply Rejection Ratio PSRR 90 105 dB TA = 25°C; VS = 2.0V to 12V, VCM = VO = 0.5V 3
Output Voltage Swing Low No Load VOL 6 12 mV TA = 25°C; VS = 5V, 0V; No Load 3
Output Voltage Swing Low ISINK=0.5mA VOL 40 70 mV TA = 25°C; VS = 5V, 0V; ISINK = 0.5mA 3
Output Voltage Swing Low ISINK=2.5mA VOL 110 200 mV TA = 25°C; VS = 5V, 0V; ISINK = 2.5mA 3
Supply Current per Amplifier IS 340 520 µA TA = 25°C; VS = 5V, 0V 3
Input Offset Voltage (LT1366/LT1368) VCM=VCC over temperature VOS 200 575 µV 0°C < TA < 70°C; VS = 5V, 0V; VCM = VCC 4
Input Offset Voltage (LT1366/LT1368) VCM=VEE over temperature VOS 200 575 µV 0°C < TA < 70°C; VS = 5V, 0V; VCM = VEE 4
Input Offset Voltage Shift (LT1366/LT1368) over temperature ∆VOS 200 425 µV 0°C < TA < 70°C; VS = 5V, 0V; VCM = VEE to VCC 4
Input Offset Voltage Match (Channel to Channel) over temperature ∆VOS 250 900 µV 0°C < TA < 70°C; VS = 5V, 0V; VCM = VEE, VCC (Notes 4, 5) 4
Input Offset Voltage Drift VOS TC 2 6 µV/°C 0°C < TA < 70°C; VS = 5V, 0V (Note 3) 4
Input Bias Current VCM=VCC over temperature IB 0 15 45 nA 0°C < TA < 70°C; VS = 5V, 0V; VCM = VCC 4
Input Bias Current VCM=VEE over temperature IB -45 -10 0 nA 0°C < TA < 70°C; VS = 5V, 0V; VCM = VEE 4
Input Bias Current Shift over temperature ∆IB 25 90 nA 0°C < TA < 70°C; VS = 5V, 0V; VCM = VEE to VCC 4
Input Offset Current VCM=VCC over temperature IOS 2 15 nA 0°C < TA < 70°C; VS = 5V, 0V; VCM = VCC 4
Input Offset Current VCM=VEE over temperature IOS 1 15 nA 0°C < TA < 70°C; VS = 5V, 0V; VCM = VEE 4
Input Offset Current Shift over temperature ∆IOS 2 15 nA 0°C < TA < 70°C; VS = 5V, 0V; VCM = VEE to VCC 4
Large-Signal Voltage Gain over temperature AVOL 250 2000 V/mV 0°C < TA < 70°C; VS = 5V, 0V; VO = 50mV to 4.8V, RL = 10k 4
Common Mode Rejection Ratio (LT1366/LT1368) over temperature CMRR 80 87 dB 0°C < TA < 70°C; VS = 5V, 0V; VCM = VEE to VCC 4
Power Supply Rejection Ratio over temperature PSRR 88 105 dB 0°C < TA < 70°C; VS = 2.3V to 12V, VCM = VO = 0.5V 4
Output Voltage Swing Low No Load over temperature VOL 9 14 mV 0°C < TA < 70°C; VS = 5V, 0V; No Load 4
Output Voltage Swing Low ISINK=0.5mA over temperature VOL 45 80 mV 0°C < TA < 70°C; VS = 5V, 0V; ISINK = 0.5mA 4
Output Voltage Swing Low ISINK=2.5mA over temperature VOL 120 230 mV 0°C < TA < 70°C; VS = 5V, 0V; ISINK = 2.5mA 4
Supply Current per Amplifier over temperature IS 385 540 µA 0°C < TA < 70°C; VS = 5V, 0V 4
Input Offset Voltage (LT1366/LT1368) VCM=VCC 3V VOS 150 475 µV TA = 25°C; VS = 3V, 0V; VCM = VCC 4
Large-Signal Voltage Gain 3V AVOL 250 1500 V/mV TA = 25°C; VS = 3V, 0V; VO = 50mV to 2.8V, RL = 10k 5
Supply Current per Amplifier 3V IS 330 500 µA TA = 25°C; VS = 3V, 0V 5
Input Offset Voltage (LT1366/LT1368) VCM=VCC ±15V VOS 200 700 µV TA = 25°C; VS = ±15V; VCM = VCC 6
Input Offset Voltage (LT1366/LT1368) VCM=VEE ±15V VOS 200 700 µV TA = 25°C; VS = ±15V; VCM = VEE 6
Large-Signal Voltage Gain ±15V AVOL 1000 10000 V/mV TA = 25°C; VS = ±15V; VO = -14.7V to 14.7V, RL = 10k 6
Common Mode Rejection Ratio (LT1366/LT1368) ±15V CMRR 95 106 dB TA = 25°C; VS = ±15V; VCM = VEE to VCC 6
Power Supply Rejection Ratio ±15V PSRR 90 110 dB TA = 25°C; VS = ±5V to ±15V 6
Supply Current per Amplifier ±15V IS 370 550 µA TA = 25°C; VS = ±15V 6
Gain-Bandwidth Product (LT1366) AV=1000 GBW 0.4 MHz TA = 25°C; VS = 5V, 0V; AV = 1000 3
Settling Time (LT1366) AV=1, VSTEP=4V to 0.1% tS 30 µs TA = 25°C; VS = 5V, 0V; AV = 1, VSTEP = 4V to 0.1% 3
Input Noise Voltage Density en 29 nV/√Hz f = 1kHz 3
Input Noise Current Density in 0.07 pA/√Hz f = 1kHz 3
Input Capacitance CIN 12 pF 3
Slew Rate (LT1366/LT1367) ±15V SR 0.13 V/µs VS = ±15V; AV = -1, RL = Open, VO = ±10V, Measured at VO = ±5V 6

CAD (KiCad official)

  • Symbol: LT1366CN8#PBF
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: lt1366cn8-pbf-etched.step / lt1366cn8-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt1366cn8-pbf.step / lt1366cn8-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (20 pp, sha256 459dbd8a27d1f385, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF