component
MSP430F6724AIPZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F6724AIPZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
MSP430F6724AIPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SD0P0 | input | SD24_B positive analog input for converter 0; diode current at this pin is limited to 2 mA and a protection diode connects to VCC (not VSS). |
| 2 | SD0N0 | input | SD24_B negative analog input for converter 0; diode current at this pin is limited to 2 mA and a protection diode connects to VCC (not VSS). |
| 3 | SD1P0 | input | SD24_B positive analog input for converter 1; diode current at this pin is limited to 2 mA and a protection diode connects to VCC (not VSS). |
| 4 | SD1N0 | input | SD24_B negative analog input for converter 1; diode current at this pin is limited to 2 mA and a protection diode connects to VCC (not VSS). |
| 5 | NC | unconnected | Not connected on MSP430F672xA devices; the SD24_B converter 2 positive input exists only on MSP430F673xA. |
| 6 | NC | unconnected | Not connected on MSP430F672xA devices; the SD24_B converter 2 negative input exists only on MSP430F673xA. |
| 7 | VREF | power_in | SD24_B external reference voltage input/output terminal used by the converters. |
| 8 | AVSS | power_in | Analog ground supply for the analog modules. |
| 9 | AVCC | power_in | Analog power supply; TI recommends powering AVCC and DVCC from the same source with at most 0.3 V difference during power-up and operation. |
| 10 | VASYS | power_in | Analog power supply selected among AVCC, AUXVCC1 and AUXVCC2; the recommended CVSYS capacitor must be connected (see Table 5-18). |
| 11 | P9.1/A5 | bidirectional | General-purpose digital I/O P9.1 (LVCMOS, DVCC) that doubles as ADC10_A analog input A5; setting P9SEL disables the output driver and input Schmitt trigger. |
| 12 | P9.2/A4 | bidirectional | General-purpose digital I/O P9.2 (LVCMOS, DVCC) that doubles as ADC10_A analog input A4; setting P9SEL disables the output driver and input Schmitt trigger. |
| 13 | P9.3/A3 | bidirectional | General-purpose digital I/O P9.3 (LVCMOS, DVCC) that doubles as ADC10_A analog input A3; setting P9SEL disables the output driver and input Schmitt trigger. |
| 14 | P1.0/PM_TA0.0/VeREF-/A2 | bidirectional | General-purpose digital I/O with port interrupt; mappable Timer_A TA0 CCR0 capture/compare, negative ADC reference VeREF- and ADC10_A analog input A2. |
| 15 | P1.1/PM_TA0.1/VeREF+/A1 | bidirectional | General-purpose digital I/O with port interrupt; mappable Timer_A TA0 CCR1 capture/compare, positive ADC reference VeREF+ and ADC10_A analog input A1. |
| 16 | P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0 | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A0 UART receive or SPI slave-out/master-in and ADC10_A analog input A0. |
| 17 | P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03 | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A0 UART transmit or SPI slave-in/master-out, and R03 the lowest analog LCD voltage (V5) port. |
| 18 | AUXVCC2 | power_in | Auxiliary power supply AUXVCC2, one of the two auxiliary supplies the device can switch to when the primary supply fails. |
| 19 | AUXVCC1 | power_in | Auxiliary power supply AUXVCC1, one of the two auxiliary supplies the device can switch to when the primary supply fails. |
| 20 | VDSYS | power_in | Digital power supply selected between DVCC, AUXVCC1 and AUXVCC2; it must be connected externally on board and the recommended CVSYS capacitor connected (see Table 5-18). |
| 21 | DVCC | power_in | Digital power supply; TI recommends powering DVCC and AVCC from the same source with at most 0.3 V difference during power-up and operation. |
| 22 | DVSS | power_in | Digital ground supply. |
| 23 | VCORE | power_out | Regulated core power supply for internal use only; no external DC loading or voltage may be applied and only the recommended CVCORE (470 nF) capacitor should be connected. |
| 24 | XIN | input | Input terminal for the 32 kHz crystal oscillator (LVCMOS, DVCC). |
| 25 | XOUT | output | Output terminal for the crystal oscillator; leave open when used as a dedicated XOUT pin. |
| 26 | AUXVCC3 | power_in | Auxiliary power supply AUXVCC3 dedicated to the backup subsystem (XT1, RTC_C and backup RAM). |
| 27 | P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13 | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A1 UART receive or SPI slave-out/master-in, LCD external reference LCDREF, and R13 third most positive LCD voltage port. |
| 28 | P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23 | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A1 UART transmit or SPI slave-in/master-out, and R23 second most positive LCD voltage port. |
| 29 | LCDCAP/R33 | bidirectional | LCD capacitor connection, and R33 the most positive analog LCD voltage (V1) port; this pin must be connected to DVSS if not used. |
| 30 | P8.4/TA1.0 | bidirectional | General-purpose digital I/O P8.4 with alternate Timer_A TA1 CCR0 capture input / compare output TA1.0. |
| 31 | P8.5/TA1.1 | bidirectional | General-purpose digital I/O P8.5 with alternate Timer_A TA1 CCR1 capture input / compare output TA1.1. |
| 32 | COM0 | output | LCD common output COM0 for the LCD backplane. |
| 33 | COM1 | output | LCD common output COM1 for the LCD backplane. |
| 34 | COM2 | output | LCD common output COM2 for the LCD backplane. |
| 35 | COM3 | output | LCD common output COM3 for the LCD backplane. |
| 36 | P1.6/PM_UCA0CLK/COM4 | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A0 clock input/output, or LCD common output COM4 when enabled. |
| 37 | P1.7/PM_UCB0CLK/COM5 | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_B0 clock input/output, or LCD common output COM5 when enabled. |
| 38 | P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6 | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_B0 SPI slave-out/master-in or I2C clock (open drain), or LCD common output COM6. |
| 39 | P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7 | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_B0 SPI slave-in/master-out or I2C data (open drain), or LCD common output COM7. |
| 40 | P8.6/TA2.0 | bidirectional | General-purpose digital I/O P8.6 with alternate Timer_A TA2 CCR0 capture input / compare output TA2.0. |
| 41 | P8.7/TA2.1 | bidirectional | General-purpose digital I/O P8.7 with alternate Timer_A TA2 CCR1 capture input / compare output TA2.1. |
| 42 | P9.0/TACLK/RTCCLK | bidirectional | General-purpose digital I/O P9.0 with alternate Timer_A clock input TACLK or RTC_C clock output RTCCLK. |
| 43 | P2.2/PM_UCA2RXD/PM_UCA2SOMI | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A2 UART receive or SPI slave-out/master-in. |
| 44 | P2.3/PM_UCA2TXD/PM_UCA2SIMO | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A2 UART transmit or SPI slave-in/master-out. |
| 45 | P2.4/PM_UCA1CLK | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A1 clock input/output. |
| 46 | P2.5/PM_UCA2CLK | bidirectional | General-purpose digital I/O with port interrupt; mappable eUSCI_A2 clock input/output. |
| 47 | P2.6/PM_TA1.0 | bidirectional | General-purpose digital I/O with port interrupt; mappable Timer_A TA1 CCR0 capture/compare. |
| 48 | P2.7/PM_TA1.1 | bidirectional | General-purpose digital I/O with port interrupt; mappable Timer_A TA1 CCR1 capture/compare. |
| 49 | P3.0/PM_TA2.0/BSL_TX | bidirectional | General-purpose digital I/O with mappable Timer_A TA2 CCR0 capture/compare, and BSL bootloader data transmit BSL_TX. |
| 50 | P3.1/PM_TA2.1/BSL_RX | bidirectional | General-purpose digital I/O with mappable Timer_A TA2 CCR1 capture/compare, and BSL bootloader data receive BSL_RX. |
| 51 | P3.2/PM_TACLK/PM_RTCCLK | bidirectional | General-purpose digital I/O with mappable Timer_A clock input TACLK or RTC_C clock output RTCCLK. |
| 52 | P3.3/PM_TA0.2 | bidirectional | General-purpose digital I/O with mappable Timer_A TA0 CCR2 capture/compare. |
| 53 | P3.4/PM_SDCLK/S39 | bidirectional | General-purpose digital I/O with mappable SD24_B bit-stream clock input/output, or LCD segment output S39 when enabled. |
| 54 | P3.5/PM_SD0DIO/S38 | bidirectional | General-purpose digital I/O with mappable SD24_B converter 0 bit-stream data input/output, or LCD segment output S38 when enabled. |
| 55 | P3.6/PM_SD1DIO/S37 | bidirectional | General-purpose digital I/O with mappable SD24_B converter 1 bit-stream data input/output, or LCD segment output S37 when enabled. |
| 56 | P3.7/PM_NONE/S36 | bidirectional | On MSP430F672xA devices this is general-purpose digital I/O P3.7 with no mappable SD24_B function (PM_NONE), or LCD segment output S36 when enabled. |
| 57 | P4.0/S35 | bidirectional | General-purpose digital I/O P4.0, or LCD segment output S35 when enabled. |
| 58 | P4.1/S34 | bidirectional | General-purpose digital I/O P4.1, or LCD segment output S34 when enabled. |
| 59 | P4.2/S33 | bidirectional | General-purpose digital I/O P4.2, or LCD segment output S33 when enabled. |
| 60 | P4.3/S32 | bidirectional | General-purpose digital I/O P4.3, or LCD segment output S32 when enabled. |
| 61 | P4.4/S31 | bidirectional | General-purpose digital I/O P4.4, or LCD segment output S31 when enabled. |
| 62 | P4.5/S30 | bidirectional | General-purpose digital I/O P4.5, or LCD segment output S30 when enabled. |
| 63 | P4.6/S29 | bidirectional | General-purpose digital I/O P4.6, or LCD segment output S29 when enabled. |
| 64 | P4.7/S28 | bidirectional | General-purpose digital I/O P4.7, or LCD segment output S28 when enabled. |
| 65 | P5.0/S27 | bidirectional | General-purpose digital I/O P5.0, or LCD segment output S27 when enabled. |
| 66 | P5.1/S26 | bidirectional | General-purpose digital I/O P5.1, or LCD segment output S26 when enabled. |
| 67 | P5.2/S25 | bidirectional | General-purpose digital I/O P5.2, or LCD segment output S25 when enabled. |
| 68 | P5.3/S24 | bidirectional | General-purpose digital I/O P5.3, or LCD segment output S24 when enabled. |
| 69 | P5.4/S23 | bidirectional | General-purpose digital I/O P5.4, or LCD segment output S23 when enabled. |
| 70 | P5.5/S22 | bidirectional | General-purpose digital I/O P5.5, or LCD segment output S22 when enabled. |
| 71 | P5.6/S21 | bidirectional | General-purpose digital I/O P5.6, or LCD segment output S21 when enabled. |
| 72 | P5.7/S20 | bidirectional | General-purpose digital I/O P5.7, or LCD segment output S20 when enabled. |
| 73 | P6.0/S19 | bidirectional | General-purpose digital I/O P6.0, or LCD segment output S19 when enabled. |
| 74 | DVSYS | power_in | Digital power supply for the I/Os; it must be connected externally on board for proper device operation. |
| 75 | DVSS | power_in | Digital ground supply. |
| 76 | P6.1/S18 | bidirectional | General-purpose digital I/O P6.1, or LCD segment output S18 when enabled. |
| 77 | P6.2/S17 | bidirectional | General-purpose digital I/O P6.2, or LCD segment output S17 when enabled. |
| 78 | P6.3/S16 | bidirectional | General-purpose digital I/O P6.3, or LCD segment output S16 when enabled. |
| 79 | P6.4/S15 | bidirectional | General-purpose digital I/O P6.4, or LCD segment output S15 when enabled. |
| 80 | P6.5/S14 | bidirectional | General-purpose digital I/O P6.5, or LCD segment output S14 when enabled. |
| 81 | P6.6/S13 | bidirectional | General-purpose digital I/O P6.6, or LCD segment output S13 when enabled. |
| 82 | P6.7/S12 | bidirectional | General-purpose digital I/O P6.7, or LCD segment output S12 when enabled. |
| 83 | P7.0/S11 | bidirectional | General-purpose digital I/O P7.0, or LCD segment output S11 when enabled. |
| 84 | P7.1/S10 | bidirectional | General-purpose digital I/O P7.1, or LCD segment output S10 when enabled. |
| 85 | P7.2/S9 | bidirectional | General-purpose digital I/O P7.2, or LCD segment output S9 when enabled. |
| 86 | P7.3/S8 | bidirectional | General-purpose digital I/O P7.3, or LCD segment output S8 when enabled. |
| 87 | P7.4/S7 | bidirectional | General-purpose digital I/O P7.4, or LCD segment output S7 when enabled. |
| 88 | P7.5/S6 | bidirectional | General-purpose digital I/O P7.5, or LCD segment output S6 when enabled. |
| 89 | P7.6/S5 | bidirectional | General-purpose digital I/O P7.6, or LCD segment output S5 when enabled. |
| 90 | P7.7/S4 | bidirectional | General-purpose digital I/O P7.7, or LCD segment output S4 when enabled. |
| 91 | P8.0/S3 | bidirectional | General-purpose digital I/O P8.0, or LCD segment output S3 when enabled. |
| 92 | P8.1/S2 | bidirectional | General-purpose digital I/O P8.1, or LCD segment output S2 when enabled. |
| 93 | P8.2/S1 | bidirectional | General-purpose digital I/O P8.2, or LCD segment output S1 when enabled. |
| 94 | P8.3/S0 | bidirectional | General-purpose digital I/O P8.3, or LCD segment output S0 when enabled. |
| 95 | TEST/SBWTCK | input | Test mode pin that selects digital I/O on the JTAG pins and always has an internal pulldown enabled; SBWTCK is the Spy-Bi-Wire input clock on this pin. |
| 96 | PJ.0/SMCLK/TDO | bidirectional | General-purpose digital I/O PJ.0, with SMCLK clock output and JTAG test data output TDO as alternate functions; leave open when used as JTAG. |
| 97 | PJ.1/MCLK/TDI/TCLK | bidirectional | General-purpose digital I/O PJ.1, with MCLK clock output and JTAG test data input TDI/TCLK as alternate functions; leave open when used as JTAG. |
| 98 | PJ.2/ADC10CLK/TMS | bidirectional | General-purpose digital I/O PJ.2, with ADC10_A clock output and JTAG test mode select TMS as alternate functions; leave open when used as JTAG. |
| 99 | PJ.3/ACLK/TCK | bidirectional | General-purpose digital I/O PJ.3, with ACLK clock output and JTAG test clock TCK as alternate functions; leave open when used as JTAG. |
| 100 | RST/NMI/SBWTDIO | input | Reset input, active low, with internal pullup enabled by default when configured as reset; also the NMI input and Spy-Bi-Wire data input/output SBWTDIO. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
MSP430F6724AIPZR - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
msp430f6724aipzr-etched.step/msp430f6724aipzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f6724aipzr.step/msp430f6724aipzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (168 pp, sha256
9f50329e4202500f, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).