LT3975EMSE#PBF from Analog Devices, in a MSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FB	input	FB regulates to 1.197V; connect the feedback divider tap here and a phase lead capacitor (typically 10pF) between FB and the output.
2	SS	passive	A soft-start capacitor from SS to ground slowly ramps the peak current limit at start-up, with an internal 1.8µA pull-up; float the pin to disable soft-start.
3	OUT	input	OUT is the input to the dropout comparator that maintains a minimum 500mV between VIN and OUT; connect it to the output when the programmed output voltage is below 16V.
4	BOOST	power_in	BOOST provides a drive voltage higher than the input voltage to the internal bipolar NPN power switch.
5	SW	output	SW is the output of the internal power switch and connects to the inductor, catch diode, and boost capacitor.
6	SW	output	SW is the output of the internal power switch and connects to the inductor, catch diode, and boost capacitor.
7	SW	output	SW is the output of the internal power switch and connects to the inductor, catch diode, and boost capacitor.
8	NC	unconnected	No connect; this pin is not connected to internal circuitry.
9	NC	unconnected	No connect; this pin is not connected to internal circuitry.
10	VIN	power_in	VIN supplies the internal circuitry and power switch and must be locally bypassed.
11	VIN	power_in	VIN supplies the internal circuitry and power switch and must be locally bypassed.
12	VIN	power_in	VIN supplies the internal circuitry and power switch and must be locally bypassed.
13	EN	input	EN high enables the part and low shuts it down; threshold is 1.08V rising and 1.02V falling, accurate only when VIN is above 4.3V, and internal UVLO shuts down the part below 3.9V.
14	RT	passive	A resistor from RT to ground sets the switching frequency.
15	PG	output	PG is an open-drain power good output that stays low until FB is within 8.4% of the final regulation voltage and is valid when VIN is above 2V.
16	SYNC	input	SYNC is the external clock synchronization input; ground it for Burst Mode operation at low loads, and do not float it.
17	GND	power_in	Exposed pad ground that must be soldered to the PCB.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	MSOP-16-EP
Category	Power Management ICs
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Minimum Input Voltage		4.3			V	l, full operating temperature range	2
Dropout Comparator Threshold (VIN, OUT)		430	500	570	mV	Falling	2
Dropout Comparator Threshold Hysteresis			25		mV		2
Quiescent Current from VIN	IQ		0.7		µA	VEN Low	2
Quiescent Current from VIN	IQ		1.6		µA	VEN High, VSYNC Low	2
Quiescent Current from VIN	IQ		1.3	2.7	µA	VEN High, VSYNC Low, l	2
FB Pin Current	IFB		0.1	12	nA	VFB = 1.5V, l	2
Feedback Voltage	VFB	1.173	1.197	1.222	V	l	2
Feedback Voltage	VFB	1.183	1.197	1.212	V		2
FB Voltage Line Regulation			0.0003	0.01	%/V	4.3V < VIN < 40V	2
Switching Frequency	fSW	1.8	2.25	2.7	MHz	RT = 11.8k	2
Switching Frequency	fSW	0.8	1	1.2	MHz	RT = 41.2k	2
Switching Frequency	fSW	160	200	240	kHz	RT = 294k	2
Minimum Switch On-Time	tON(MIN)			105	ns		2
Minimum Switch Off-Time	tOFF(MIN)		150	200	ns	Note 4	2
Switch Current Limit	ILIM	4	5.4	6.8	A	VFB = 1V	3
Foldback Switch Current Limit	ILIM		3.3		A	VFB = 0V	3
Switch VCESAT	VCESAT			80	mV	ISW = 1A	3
Switch Leakage Current			0.02	1	μA		3
Boost Schottky Forward Voltage	VF			730	mV	ISH = 100mA	3
Boost Schottky Reverse Leakage	IR		0.02	2	μA	VREVERSE = 12V	3
Minimum Boost Voltage		1.3		1.8	V	l	3
BOOST Pin Current			20	32	mA	ISW = 1A, VBOOST, VSW = 3V	3
EN Voltage Threshold		0.92	1.02	1.12	V	EN Falling, VIN ≥ 4.3V, l	3
EN Voltage Hysteresis			60		mV		3
EN Pin Current			0.2	20	nA		3
PG Threshold Offset from VFB		5	8.4	13	%	VFB Falling	3
PG Hysteresis as % of Output Voltage			1.7		%		3
PG Leakage			0.02	1	µA	VPG = 3V	3
PG Sink Current		125		480	μA	VPG = 0.4V, l	3
SYNC Low Threshold			0.6	1	V		3
SYNC High Threshold		1.18		1.5	V		3
SYNC Pin Current			0.1		nA	VSYNC = 6V	3
SS Source Current		0.9	1.8	2.6	μA	VSS = 0.5V	3
BOOST Pin Above SW Pin				30	V		2
FB, RT, SYNC, SS Voltage				6	V		2
PG Voltage				30	V		2
OUT Voltage				16	V		2
Operating Junction Temperature Range (LT3975E)	TJ	-40		125	°C	LT3975E	2
Storage Temperature Range	TSTG	-65		150	°C		2
Thermal Resistance, Junction to Ambient	θJA		40		°C/W	MSE package	2

CAD (KiCad official)

Symbol: LT3975EMSE#PBF
Footprint: Package_SO:MSOP-16-1EP_3x4.039mm_P0.5mm_EP1.651x2.845mm
3D model: MSOP-16-EP (KiCad packages3D, STEP)
3D model files: lt3975emse-pbf-etched.step / lt3975emse-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3975emse-pbf.step / lt3975emse-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 d1c511aec8b7e702, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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LT3975EMSE#PBF

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