component
CD4060DM
Public Unreviewedby Ray
HGSEMI Counters / Dividers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4060DM
HGSEMI · Counters / Dividers · SOP-16
CD4060DM from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Counter output stage 12. CMOS push-pull output driven by the 14-stage binary ripple counter; toggles at fCLK/2^12. |
| 2 | Q13 | output | Counter output stage 13. CMOS push-pull output; toggles at fCLK/2^13. |
| 3 | Q14 | output | Counter output stage 14 (final stage). CMOS push-pull output; toggles at fCLK/2^14. |
| 4 | Q6 | output | Counter output stage 6. CMOS push-pull output; toggles at fCLK/2^6. |
| 5 | Q5 | output | Counter output stage 5. CMOS push-pull output; toggles at fCLK/2^5. |
| 6 | Q7 | output | Counter output stage 7. CMOS push-pull output; toggles at fCLK/2^7. |
| 7 | Q4 | output | Counter output stage 4. CMOS push-pull output; toggles at fCLK/2^4. |
| 8 | VSS | power_in | Negative supply / ground reference (0 V). Recommended supply range VDD-VSS = 3 V to 15 V. |
| 9 | Φ0 | output | Oscillator buffered clock output (Phi0). Connects to the external RC or crystal network together with pins 10 and 11 to form the on-chip oscillator. |
| 10 | Φ0_bar | output | Inverted oscillator output (Phi0 with overbar). Used with pin 9 (Φ0) and pin 11 (ΦI) to bias the external RC or crystal oscillator network. |
| 11 | ΦI | input | Oscillator/clock input (PhiI). Schmitt-trigger input; tied to the external RC or crystal network, or driven directly by an external clock source. |
| 12 | RESET | input | Active-high asynchronous master reset. When high, all counter stages are cleared to 0 and the internal oscillator is disabled. Should be tied to VSS for normal counting operation. |
| 13 | Q9 | output | Counter output stage 9. CMOS push-pull output; toggles at fCLK/2^9. |
| 14 | Q8 | output | Counter output stage 8. CMOS push-pull output; toggles at fCLK/2^8. |
| 15 | Q10 | output | Counter output stage 10. CMOS push-pull output; toggles at fCLK/2^10. |
| 16 | VDD | power_in | Positive supply pin. Recommended VDD-VSS operating range 3 V to 15 V; absolute max 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Ordering variants
Same part, different packaging or reel option.
CD4060DM/TRCD4060DMDECD4060DMDNCD4060DMT/TR
CAD (KiCad official)
- Symbol:
CD4060DM - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (9 pp, sha256
429b5643241501b2, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).