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Contents

README

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CJQ60P05

Changjing · MOSFETs · SOP-8

CJQ60P05 from Changjing, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the P-channel MOSFET, tied internally with pins 2 and 3; drain-source rating is -60V.
2 S passive Source of the P-channel MOSFET, tied internally with pins 1 and 3; continuous drain current is -5A.
3 S passive Source of the P-channel MOSFET, tied internally with pins 1 and 2; gate-source voltage limit is ±20V.
4 G input Gate of the P-channel MOSFET; gate-source voltage limit is ±20V and threshold is -1.5 to -3.5V at ID=-250µA.
5 D passive Drain of the MOSFET, tied internally with pins 6, 7 and 8; VDS -60V, ID -5A, RDS(ON) below 80mΩ at VGS=-10V.
6 D passive Drain of the MOSFET, tied internally with pins 5, 7 and 8; pulsed drain current is -25A.
7 D passive Drain of the MOSFET, tied internally with pins 5, 6 and 8; drain-source voltage is -60V maximum.
8 D passive Drain of the MOSFET, tied internally with pins 5, 6 and 7; continuous drain current is -5A.

Key specifications

Parameter Value
Manufacturer Changjing
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS -60 V 1
Gate-Source Voltage VGS -20 20 V 1
Drain Current-Continuous ID -5 A 1
Pulsed Drain Current IDM -25 A Note 1: repetitive rating, pulse width limited by maximum junction temperature 1
Operating Junction Temperature TJ 150 °C 1
Storage Temperature Range TSTG -55 150 °C 1
Lead Temperature for Soldering Purposes TL 260 °C 1/8 inch from case for 10 s 1
Thermal Resistance, Junction-to-Ambient RθJA 100 °C/W Surface mounted on FR4 board, t ≤ 10 sec (Note 2) 1
Drain-Source Breakdown Voltage BVDSS -60 V VGS=0V ID=-250µA 2
Zero Gate Voltage Drain Current IDSS -1 µA VDS=-60V,VGS=0V 2
Gate-Body Leakage Current IGSS -100 100 nA VGS=±20V,VDS=0V 2
Gate Threshold Voltage VGS(th) -3.5 -1.5 V VDS=VGS,ID=-250µA 2
Drain-Source On-State Resistance RDS(ON) 80 mΩ VGS=-10V, ID=-5A 2
Diode Forward Current IS -5 A 2
Diode Forward Voltage VSD -1.2 V VGS=0V,IS=-3A 2
Forward Transconductance gFS 5 S VDS=-15V,ID=-5A 2
Input Capacitance Clss 1450 pF VDS=-20V,VGS=0V, f=1.0MHz 2
Output Capacitance Coss 145 pF VDS=-20V,VGS=0V, f=1.0MHz 2
Reverse Transfer Capacitance Crss 110 pF VDS=-20V,VGS=0V, f=1.0MHz 2
Turn-on Delay Time td(on) 8 ns VDD=-30V, RL=30Ω, VGS=-10V, RGEN=6Ω 2
Turn-on Rise Time tr 9 ns VDD=-30V, RL=30Ω, VGS=-10V, RGEN=6Ω 2
Turn-Off Delay Time td(off) 65 ns VDD=-30V, RL=30Ω, VGS=-10V, RGEN=6Ω 2
Turn-Off Fall Time tf 30 ns VDD=-30V, RL=30Ω, VGS=-10V, RGEN=6Ω 2
Total Gate Charge Qg 26 nC VDS=-30V,ID=-5A, VGS=-10V 2
Gate-Source Charge Qgs 4.5 nC VDS=-30V,ID=-5A, VGS=-10V 2
Gate-Drain Charge Qgd 7 nC VDS=-30V,ID=-5A, VGS=-10V 2

CAD (KiCad official)

  • Symbol: CJQ60P05
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: cjq60p05-etched.step / cjq60p05-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cjq60p05.step / cjq60p05.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Changjing datasheet (5 pp, sha256 2758e73f1c077652, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF