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CD74HC4094M96
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74HC4094M96
Texas Instruments · Shift Registers · SOIC-16
CD74HC4094M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STROBE | input | Strobe input: when high, the data in each shift register stage is transferred to the storage register. |
| 2 | DATA | input | Serial data input to the 8-stage shift register, shifted in on positive clock transitions. |
| 3 | CP | input | Clock input: data is shifted on positive clock transitions, and QS1 and QS2 provide serial outputs on the positive and following negative clock edges. |
| 4 | Q0 | tri_state | Three-state parallel output Q0; data appears here when OE is high and the outputs may be connected directly to common bus lines. |
| 5 | Q1 | tri_state | Three-state parallel output Q1; data appears here when OE is high and the outputs may be connected directly to common bus lines. |
| 6 | Q2 | tri_state | Three-state parallel output Q2; data appears here when OE is high and the outputs may be connected directly to common bus lines. |
| 7 | Q3 | tri_state | Three-state parallel output Q3; data appears here when OE is high and the outputs may be connected directly to common bus lines. |
| 8 | GND | power_in | Ground reference pin. |
| 9 | QS1 | output | Serial output available on positive clock edges, allowing high-speed operation in cascaded systems where the clock rise time is fast. |
| 10 | QS2 | output | Serial output available on the next negative clock edge, provided for cascading when the clock rise time is slow. |
| 11 | Q7 | tri_state | Three-state parallel output Q7; data appears here when OE is high and the outputs may be connected directly to common bus lines. |
| 12 | Q6 | tri_state | Three-state parallel output Q6; data appears here when OE is high and the outputs may be connected directly to common bus lines. |
| 13 | Q5 | tri_state | Three-state parallel output Q5; data appears here when OE is high and the outputs may be connected directly to common bus lines. |
| 14 | Q4 | tri_state | Three-state parallel output Q4; data appears here when OE is high and the outputs may be connected directly to common bus lines. |
| 15 | OE | input | Output enable: parallel outputs Q0 to Q7 show the storage register data only while OE is high; when low they are high-impedance. |
| 16 | VCC | power_in | Supply voltage: 2 V to 6 V for HC types (4.5 V to 5.5 V for HCT types), per the operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, HC types | VCC | 2 | 6 | V | HC types | 4 | |
| Temperature range | TA | -55 | 125 | °C | 4 | ||
| DC input or output voltage | VI, VO | 0 | V | Upper limit VCC | 4 | ||
| DC supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| DC input diode current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| DC output diode current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| DC output source or sink current per output pin | IO | -25 | 25 | mA | VO > -0.5 V or VO < VCC + 0.5 V | 4 | |
| DC VCC or ground current | ICC | -50 | 50 | mA | 4 | ||
| Maximum storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Maximum junction temperature (plastic package) | TJ | 150 | °C | 4 | |||
| Maximum lead temperature (soldering 10 s) | 300 | °C | 10 s, SOIC lead tips only | 4 | |||
| High level input voltage, VCC = 2 V | VIH | 1.5 | V | VCC = 2 V; TA = -55 to 125 °C | 4 | ||
| High level input voltage, VCC = 4.5 V | VIH | 3.15 | V | VCC = 4.5 V; TA = -55 to 125 °C | 4 | ||
| High level input voltage, VCC = 6 V | VIH | 4.2 | V | VCC = 6 V; TA = -55 to 125 °C | 4 | ||
| Low level input voltage, VCC = 2 V | VIL | 0.5 | V | VCC = 2 V; TA = -55 to 125 °C | 4 | ||
| Low level input voltage, VCC = 4.5 V | VIL | 1.35 | V | VCC = 4.5 V; TA = -55 to 125 °C | 4 | ||
| Low level input voltage, VCC = 6 V | VIL | 1.8 | V | VCC = 6 V; TA = -55 to 125 °C | 4 | ||
| High level output voltage, CMOS loads, VCC = 2 V | VOH | 1.9 | V | VI = VIH or VIL; IO = -0.02 mA; TA = -55 to 125 °C | 4 | ||
| High level output voltage, CMOS loads, VCC = 4.5 V | VOH | 4.4 | V | VI = VIH or VIL; IO = -0.02 mA; TA = -55 to 125 °C | 4 | ||
| High level output voltage, CMOS loads, VCC = 6 V | VOH | 5.9 | V | VI = VIH or VIL; IO = -0.02 mA; TA = -55 to 125 °C | 4 | ||
| High level output voltage, TTL loads, VCC = 4.5 V | VOH | 3.7 | V | IO = -4 mA; TA = -55 to 125 °C | 4 | ||
| High level output voltage, TTL loads, VCC = 6 V | VOH | 5.2 | V | IO = -5.2 mA; TA = -55 to 125 °C | 4 | ||
| Low level output voltage, CMOS loads, VCC = 2 V | VOL | 0.1 | V | VI = VIH or VIL; IO = 0.02 mA; TA = -55 to 125 °C | 4 | ||
| Low level output voltage, CMOS loads, VCC = 4.5 V | VOL | 0.1 | V | VI = VIH or VIL; IO = 0.02 mA; TA = -55 to 125 °C | 4 | ||
| Low level output voltage, CMOS loads, VCC = 6 V | VOL | 0.1 | V | VI = VIH or VIL; IO = 0.02 mA; TA = -55 to 125 °C | 4 | ||
| Low level output voltage, TTL loads, VCC = 4.5 V | VOL | 0.4 | V | IO = 4 mA; TA = -55 to 125 °C | 4 | ||
| Low level output voltage, TTL loads, VCC = 6 V | VOL | 0.4 | V | IO = 5.2 mA; TA = -55 to 125 °C | 4 | ||
| Input leakage current | II | -1 | 1 | µA | VCC = 6 V; VI = VCC or GND; TA = -55 to 125 °C | 4 | |
| Quiescent device current | ICC | 160 | µA | VCC = 6 V; VI = VCC or GND; TA = -55 to 125 °C | 4 | ||
| Propagation delay CP to QS1, VCC = 2 V | tPLH, tPHL | 225 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay CP to QS1, VCC = 4.5 V | tPLH, tPHL | 45 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay CP to QS1, VCC = 6 V | tPLH, tPHL | 38 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay CP to QS2, VCC = 2 V | tPLH, tPHL | 205 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay CP to QS2, VCC = 4.5 V | tPLH, tPHL | 41 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay CP to QS2, VCC = 6 V | tPLH, tPHL | 35 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay CP to Qn, VCC = 2 V | tPLH, tPHL | 295 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay CP to Qn, VCC = 4.5 V | tPLH, tPHL | 59 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay CP to Qn, VCC = 6 V | tPLH, tPHL | 50 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay STR to Qn, VCC = 2 V | tPLH, tPHL | 270 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay STR to Qn, VCC = 4.5 V | tPLH, tPHL | 54 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Propagation delay STR to Qn, VCC = 6 V | tPLH, tPHL | 46 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 6 | ||
| Output enable to Qn, VCC = 2 V | tPZH, tPZL | 265 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Output enable to Qn, VCC = 4.5 V | tPZH, tPZL | 53 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Output enable to Qn, VCC = 6 V | tPZH, tPZL | 45 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Output disable to Qn, VCC = 2 V | tPHZ, tPLZ | 190 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Output disable to Qn, VCC = 4.5 V | tPHZ, tPLZ | 38 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Output disable to Qn, VCC = 6 V | tPHZ, tPLZ | 32 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Output transition time, VCC = 2 V | tTLH, tTHL | 110 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Output transition time, VCC = 4.5 V | tTLH, tTHL | 22 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Output transition time, VCC = 6 V | tTLH, tTHL | 19 | ns | CL = 50 pF; input tr, tf = 6 ns; TA = -55 to 125 °C | 7 | ||
| Maximum CP frequency, VCC = 2 V | fCL(MAX) | 4 | MHz | TA = -55 to 125 °C | 5 | ||
| Maximum CP frequency, VCC = 4.5 V | fCL(MAX) | 20 | MHz | TA = -55 to 125 °C | 5 | ||
| Maximum CP frequency, VCC = 6 V | fCL(MAX) | 24 | MHz | TA = -55 to 125 °C | 5 |
CAD (KiCad official)
- Symbol:
CD74HC4094M96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd74hc4094m96-etched.step/cd74hc4094m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc4094m96.step/cd74hc4094m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
782af67cf8c4fc66, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).