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ATTINY13-20PU
Public Made by Adomby adom
Microchip Tech MICROCHIP, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownATTINY13-20PU
Microchip Tech · MICROCHIP · DIP-8
ATTINY13-20PU from Microchip Tech, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB5 | bidirectional | Port B bit 5 used as RESET input: a low level longer than the minimum pulse length in Table 18-1 (page 115) generates a reset even without a running clock, and shorter pulses are not guaranteed to reset; the pin can also be used as a (weak) I/O pin. |
| 2 | PB3 | bidirectional | Port B bit 3 is a bidirectional I/O pin with optional internal pull-up that is tri-stated during reset, and it also serves as CLKI, ADC3 and PCINT3 alternate functions. |
| 3 | PB4 | bidirectional | Port B bit 4 is a bidirectional I/O pin with optional internal pull-up that is tri-stated during reset, and it also serves as ADC2 and PCINT4 alternate functions. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | PB0 (MOSI/AIN0/OC0A/PCINT0) | bidirectional | Port B bit 0 is a bidirectional I/O pin with symmetrical high sink and source drive and optional internal pull-up that is tri-stated during reset, and it also serves as MOSI, AIN0, OC0A and PCINT0 alternate functions. |
| 6 | PB1 (MISO/AIN1/OC0B/INT0/PCINT1) | bidirectional | Port B bit 1 is a bidirectional I/O pin with symmetrical high sink and source drive and optional internal pull-up that is tri-stated during reset, and it also serves as MISO, AIN1, OC0B, INT0 and PCINT1 alternate functions. |
| 7 | PB2 (SCK/ADC1/T0/PCINT2) | bidirectional | Port B bit 2 is a bidirectional I/O pin with symmetrical high sink and source drive and optional internal pull-up that is tri-stated during reset, and it also serves as SCK, ADC1, T0 and PCINT2 alternate functions. |
| 8 | VCC | power_in | Digital supply voltage; the ATtiny13 operating range is 2.7 - 5.5V, and 20 MHz operation requires 4.5 - 5.5V (ranges stated on page 1). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Temperature | -55 | 125 | °C | 115 | |||
| Storage Temperature | -65 | 150 | °C | 115 | |||
| Voltage on any pin except RESET with respect to Ground | -0.5 | V | Printed max is VCC+0.5V (not a number) | 115 | |||
| Voltage on RESET with respect to Ground | -0.5 | 13 | V | 115 | |||
| Maximum Operating Voltage | 6 | V | 115 | ||||
| DC Current per I/O Pin | 40 | mA | 115 | ||||
| DC Current VCC and GND Pins | 200 | mA | 115 | ||||
| Supply voltage (ATtiny13, non-V) | VCC | 2.7 | 5.5 | V | ATtiny13 (not ATtiny13V) operating voltage | 1 | |
| Industrial operating temperature range | -40 | 85 | °C | Industrial grade, ordering code 20 MHz / 2.7-5.5 V | 160 | ||
| Output Low Voltage, Pins PB0 and PB1 | VOL | 0.7 | V | IOL = 20 mA, VCC = 5V | 115 | ||
| Output Low Voltage, Pins PB0 and PB1 | VOL | 0.5 | V | IOL = 10 mA, VCC = 3V | 115 | ||
| Output Low Voltage, Pins PB2, PB3 and PB4 | VOL | 0.7 | V | IOL = 10 mA, VCC = 5V | 115 | ||
| Output Low Voltage, Pins PB2, PB3 and PB4 | VOL | 0.5 | V | IOL = 5 mA, VCC = 3V | 115 | ||
| Output High Voltage, Pins PB0 and PB1 | VOH | 4.2 | V | IOH = -20 mA, VCC = 5V | 115 | ||
| Output High Voltage, Pins PB0 and PB1 | VOH | 2.5 | V | IOH = -10 mA, VCC = 3V | 115 | ||
| Output High Voltage, Pins PB2, PB3 and PB4 | VOH | 4.2 | V | IOH = -10 mA, VCC = 5V | 115 | ||
| Output High Voltage, Pins PB2, PB3 and PB4 | VOH | 2.5 | V | IOH = -5 mA, VCC = 3V | 115 | ||
| Input Leakage Current I/O Pin (low) | ILIL | -1 | 1 | µA | VCC = 5.5V, pin low | 115 | |
| Input Leakage Current I/O Pin (high) | ILIH | -1 | 1 | µA | VCC = 5.5V, pin high | 116 | |
| Pull-Up Resistor, I/O Pin | RPU | 20 | 50 | kΩ | VCC = 5.5V, input low | 116 | |
| Pull-Up Resistor, Reset Pin | RPU | 30 | 80 | kΩ | VCC = 5.5V, input low | 116 | |
| Supply Current, Active Mode | ICC | 1.6 | 1.8 | mA | f = 4MHz, VCC = 3V | 116 | |
| Supply Current, Active Mode | ICC | 5 | 6 | mA | f = 8MHz, VCC = 5V | 116 | |
| Supply Current, Idle Mode | ICC | 0.41 | 1 | mA | f = 4MHz, VCC = 3V | 116 | |
| Supply Current, Idle Mode | ICC | 1.6 | 3 | mA | f = 8MHz, VCC = 5V | 116 | |
| Supply Current, Power-Down Mode | ICC | 5 | 10 | µA | WDT enabled, VCC = 3V | 116 | |
| Supply Current, Power-Down Mode | ICC | 0.5 | 2 | µA | WDT disabled, VCC = 3V | 116 | |
| Calibration accuracy, factory calibration | -10 | 10 | % | Target 4.8/9.6 MHz, VCC 3V, 25°C | 118 | ||
| Calibration accuracy, user calibration | -2 | 2 | % | Fixed frequency 4-5 / 8-10 MHz, fixed voltage 2.7-5.5V, fixed temperature -40°C to +85°C | 118 | ||
| Clock Frequency | 1/tCLCL | 0 | 10 | MHz | VCC = 2.7 - 5.5V | 118 | |
| Clock Frequency | 1/tCLCL | 0 | 20 | MHz | VCC = 4.5 - 5.5V | 118 | |
| Clock Period | tCLCL | 100 | ns | VCC = 2.7 - 5.5V | 118 | ||
| Clock Period | tCLCL | 50 | ns | VCC = 4.5 - 5.5V | 118 | ||
| High Time | tCHCX | 40 | ns | VCC = 2.7 - 5.5V | 118 | ||
| High Time | tCHCX | 20 | ns | VCC = 4.5 - 5.5V | 118 | ||
| Low Time | tCLCX | 40 | ns | VCC = 2.7 - 5.5V | 118 | ||
| Low Time | tCLCX | 20 | ns | VCC = 4.5 - 5.5V | 118 | ||
| Rise Time | tCLCH | 1.6 | µs | VCC = 2.7 - 5.5V | 118 | ||
| Rise Time | tCLCH | 0.5 | µs | VCC = 4.5 - 5.5V | 118 | ||
| Fall Time | tCHCL | 1.6 | µs | VCC = 2.7 - 5.5V | 118 | ||
| Fall Time | tCHCL | 0.5 | µs | VCC = 4.5 - 5.5V | 118 | ||
| Oscillator Frequency (serial programming, ATtiny13) | 1/tCLCL | 0 | 9.6 | MHz | ATtiny13, VCC = 2.7 - 5.5V | 121 | |
| Oscillator Period (serial programming, ATtiny13) | tCLCL | 104 | ns | ATtiny13, VCC = 2.7 - 5.5V | 121 | ||
| Oscillator Frequency (serial programming, ATtiny13) | 1/tCLCL | 0 | 20 | MHz | ATtiny13, VCC = 4.5V - 5.5V | 121 | |
| Oscillator Period (serial programming, ATtiny13) | tCLCL | 50 | ns | ATtiny13, VCC = 4.5V - 5.5V | 121 | ||
| Bandgap reference voltage | VBG | 1 | 1.1 | 1.2 | V | 119 | |
| Bandgap reference start-up time | tBG | 40 | 70 | µs | 119 | ||
| Input Offset Voltage | VAIO | 40 | mV | VCC = 5V, VIN = VCC / 2 | 119 | ||
| Input Leakage Current (analog comparator) | ILAC | -50 | 50 | nA | VCC = 5V, VIN = VCC / 2 | 119 | |
| Digital Propagation Delay | tDPD | 1 | 2 | CLK | VCC = 1.8 - 5.5V | 119 | |
| Conversion Time, free running | 13 | 260 | µs | Free Running Conversion | 120 | ||
| ADC Clock Frequency | 50 | 1000 | kHz | 120 | |||
| Internal Voltage Reference | VINT | 1 | 1.1 | 1.2 | V | 120 | |
| Minimum pulse width on RESET Pin | tRST | 2.5 | µs | VCC = 1.8V - 5.5V | 119 | ||
| Min Pulse Width on Brown-out Reset | tBOD | 2 | µs | 119 | |||
| Power-on Reset Threshold Voltage (rising) | VPOT | 1.2 | V | TA = -40 to +85°C | 119 | ||
| Power-on Reset Threshold Voltage (falling) | VPOT | 1.1 | V | TA = -40 to +85°C | 119 | ||
| Bandgap reference current consumption | IBG | 15 | µs | 119 | |||
| SDO valid after SCI high (high-voltage serial programming) | tSHOV | 16 | ns | TA = 25°C, VCC = 5.0V ± 10% | 122 |
CAD (KiCad official)
- Symbol:
ATTINY13-20PU - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
attiny13-20pu-etched.step/attiny13-20pu-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);attiny13-20pu.step/attiny13-20pu.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (176 pp, sha256
40026c140811adb0, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).