component
74HC107D
Public Made by Adomby adom
Nexperia Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC107D
Nexperia · Flip Flops · SOIC-14
74HC107D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1J | input | Synchronous J input of flip-flop 1, which must be stable one set-up time before the HIGH-to-LOW clock transition for predictable operation. |
| 2 | ~{1Q} | output | Complement output of flip-flop 1, the inverse of 1Q. |
| 3 | 1Q | output | True output of flip-flop 1. |
| 4 | 1K | input | Synchronous K input of flip-flop 1, which must be stable one set-up time before the HIGH-to-LOW clock transition for predictable operation. |
| 5 | 2Q | output | True output of flip-flop 2. |
| 6 | ~{2Q} | output | Complement output of flip-flop 2, the inverse of 2Q. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages. |
| 8 | 2J | input | Synchronous J input of flip-flop 2, which must be stable one set-up time before the HIGH-to-LOW clock transition for predictable operation. |
| 9 | 2CP | input | Clock input of flip-flop 2, triggered on the HIGH-to-LOW edge. |
| 10 | 2R | input | Asynchronous reset input of flip-flop 2, active LOW and independent of the clock. |
| 11 | 2K | input | Synchronous K input of flip-flop 2, which must be stable one set-up time before the HIGH-to-LOW clock transition for predictable operation. |
| 12 | 1CP | input | Clock input of flip-flop 1, triggered on the HIGH-to-LOW edge. |
| 13 | 1R | input | Asynchronous reset input of flip-flop 1, active LOW and independent of the clock. |
| 14 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 6.0 V for 74HC107 and 4.5 V to 5.5 V for 74HCT107. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 2 | 5 | 6 | V | 74HC107 column | 4 |
| input voltage (max printed as VCC) | VI | 0 | V | 4 | |||
| output voltage (max printed as VCC) | VO | 0 | V | 4 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 4 | ||
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| output current | IO | -25 | 25 | mA | VO = -0.5 V to VCC + 0.5 V | 4 | |
| supply current | ICC | 50 | mA | 4 | |||
| ground current | IGND | -50 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C; SOT108-1 (SO14) derates 10.1 mW/K above 100 °C | 4 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C (typ at 25 °C) | 5 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 3.7 | 4.32 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 5.2 | 5.81 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0.15 | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| additional supply current | ΔICC | 100 | 490 | μA | pin nCP, nJ; per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | |
| additional supply current | ΔICC | 65 | 319 | μA | pin nR; per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | |
| additional supply current | ΔICC | 60 | 294 | μA | pin nK; per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 | |
| propagation delay nCP to nQ | tpd | 52 | 240 | ns | nCP to nQ; see Fig. 4; CL = 50 pF; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| propagation delay nCP to nQ | tpd | 19 | 48 | ns | nCP to nQ; see Fig. 4; CL = 50 pF; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| propagation delay nCP to nQ | tpd | 15 | 41 | ns | nCP to nQ; see Fig. 4; CL = 50 pF; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| propagation delay nR to nQ, nQ | tpd | 52 | 235 | ns | nR to nQ, nQ; see Fig. 5; CL = 50 pF; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| propagation delay nR to nQ, nQ | tpd | 19 | 47 | ns | nR to nQ, nQ; see Fig. 5; CL = 50 pF; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| propagation delay nR to nQ, nQ | tpd | 15 | 40 | ns | nR to nQ, nQ; see Fig. 5; CL = 50 pF; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| transition time | tt | 19 | 110 | ns | nQ, nQ; see Fig. 4; CL = 50 pF; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| transition time | tt | 7 | 22 | ns | nQ, nQ; see Fig. 4; CL = 50 pF; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| transition time | tt | 6 | 19 | ns | nQ, nQ; see Fig. 4; CL = 50 pF; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| pulse width nCP input HIGH or LOW | tW | 120 | 22 | ns | nCP input, HIGH or LOW; see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| pulse width nCP input HIGH or LOW | tW | 24 | 8 | ns | nCP input, HIGH or LOW; see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| pulse width nCP input HIGH or LOW | tW | 20 | 6 | ns | nCP input, HIGH or LOW; see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 7 | |
| recovery time nR to nCP | trec | 90 | 19 | ns | nR to nCP; see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| recovery time nR to nCP | trec | 18 | 7 | ns | nR to nCP; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| recovery time nR to nCP | trec | 15 | 6 | ns | nR to nCP; see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 7 | |
| set-up time nJ, nK to nCP | tsu | 150 | 22 | ns | nJ, nK to nCP; see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| set-up time nJ, nK to nCP | tsu | 30 | 8 | ns | nJ, nK to nCP; see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| set-up time nJ, nK to nCP | tsu | 26 | 6 | ns | nJ, nK to nCP; see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 7 | |
| hold time nJ, nK to nCP | th | 3 | -6 | ns | nJ, nK to nCP; see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| hold time nJ, nK to nCP | th | 3 | -2 | ns | nJ, nK to nCP; see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| maximum frequency | fmax | 4 | 23 | MHz | nCP input; see Fig. 4; VCC = 2.0 V; -40 °C to +125 °C | 7 | |
| maximum frequency | fmax | 20 | 70 | MHz | nCP input; see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 7 | |
| maximum frequency | fmax | 24 | 85 | MHz | nCP input; see Fig. 4; VCC = 6.0 V; -40 °C to +125 °C | 7 |
CAD (KiCad official)
- Symbol:
74HC107D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
74hc107d-etched.step/74hc107d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc107d.step/74hc107d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (15 pp, sha256
6bfde9bc6830a41f, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).