MC14013BDR2G from onsemi, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	QA	output	Flip-flop A true output. CMOS push-pull output; drives two low-power TTL loads or one LS-TTL load across the rated supply range (3.0-18 V).
2	QA_N	output	Flip-flop A complementary (Q-bar) output. Always the logical inverse of QA except in the Set=Reset=1 illegal state where both outputs go high.
3	CA	input	Flip-flop A clock input. Data on DA is transferred to QA on the positive-going (rising) edge of this clock. CMOS input with diode protection; VIH >= 0.7VDD, VIL <= 0.3VDD.
4	RA	input	Flip-flop A asynchronous Direct Reset input, active-high. Forces QA=0 and QA_N=1 regardless of Clock/Data. Tie low (VSS) during normal edge-clocked operation.
5	DA	input	Flip-flop A Data input. The logic level present on DA is captured to QA on the rising edge of CA. Setup/hold: 40 ns / 40 ns at VDD=5 V (min).
6	SA	input	Flip-flop A asynchronous Direct Set input, active-high. Forces QA=1 and QA_N=0 regardless of Clock/Data. Tie low (VSS) during normal edge-clocked operation.
7	VSS	power_in	Negative supply / ground reference. All input/output voltages are referenced to VSS.
8	SB	input	Flip-flop B asynchronous Direct Set input, active-high. Forces QB=1 and QB_N=0 regardless of Clock/Data. Tie low (VSS) during normal edge-clocked operation.
9	DB	input	Flip-flop B Data input. The logic level present on DB is captured to QB on the rising edge of CB. Setup/hold: 40 ns / 40 ns at VDD=5 V (min).
10	RB	input	Flip-flop B asynchronous Direct Reset input, active-high. Forces QB=0 and QB_N=1 regardless of Clock/Data. Tie low (VSS) during normal edge-clocked operation.
11	CB	input	Flip-flop B clock input. Data on DB is transferred to QB on the positive-going (rising) edge of this clock. Max clock frequency 2 MHz @ 5 V, 5 MHz @ 10 V, 7 MHz @ 15 V.
12	QB_N	output	Flip-flop B complementary (Q-bar) output. Always the logical inverse of QB except in the Set=Reset=1 illegal state where both outputs go high.
13	QB	output	Flip-flop B true output. CMOS push-pull output; drives two low-power TTL loads or one LS-TTL load across the rated supply range (3.0-18 V).
14	VDD	power_in	Positive supply input. Operating range 3.0 V to 18 V (absolute max -0.5 to +18.0 V). Bypass locally to VSS.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	SOP-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

MC14013BDR2GDG
MC14013BDR2G
MC14013BDR2GDTR2G
MC14013BDR2GFG
MC14013BDR2GFELG

CAD (KiCad official)

Symbol: MC14013BDR2G
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOP-14 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`mc14013bdr2g.step`	195 KB	You want the bare part, or you mark your own boards.
`mc14013bdr2g-etched.step`	2.8 MB	You want the part with `MC14013BDR2G` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 704 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (8 pp, sha256 d026165b363be4d9, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF