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AD9510BCPZ

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Analog Devices Pre-ordered Chips, LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD9510BCPZ

Analog Devices · Pre-ordered Chips · LFCSP-64(9x9)

AD9510BCPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REFIN input PLL reference input, self-biased at 1.45 V to 1.75 V and requiring 150 mV p-p input sensitivity.
2 REFINB input Complementary PLL reference input, self-biased at 1.40 V to 1.60 V and used with REFIN.
3 GND power_in Ground connection for the device.
4 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
5 VCP power_in Charge pump power supply VCPS, which must be greater than or equal to VS and can be set as high as 5.5 V for VCOs requiring extended tuning range.
6 CP output Charge pump output of the PLL.
7 GND power_in Ground connection for the device.
8 GND power_in Ground connection for the device.
9 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
10 CLK2 input Clock input that connects an external VCO or VCXO to the feedback divider N, and can also serve as a generic clock input when the PLL is not used; input frequency up to 1.6 GHz.
11 CLK2B input Complementary clock input used with CLK2, with input sensitivity of 150 mV p-p.
12 GND power_in Ground connection for the device.
13 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
14 CLK1 input Clock input that drives the distribution section of the chip, with input frequency up to 1.6 GHz.
15 CLK1B input Complementary clock input used with CLK1 to drive the distribution section.
16 FUNCTION input Multipurpose input programmable as RESETB, SYNCB or PDB, internally pulled down by 30 kΩ; if left NC the part is held in reset, so connect to VS with a 1 kΩ resistor to avoid this.
17 STATUS output Output that monitors PLL status and sync status.
18 SCLK input Serial data clock input for the serial control port; write data is registered on the rising edge and read data on the falling edge, with an internal 30 kΩ pull-down.
19 SDIO bidirectional Serial data I/O pin, used as input by default or as bidirectional I/O when Register 0x00[7] = 1b.
20 SDO output Serial data output used for readback in unidirectional mode (Register 0x00[7] = 0, default).
21 CSB input Active-low serial port chip select that gates read and write cycles; it must not be left unconnected or tied low and has an internal 30 kΩ pull-down.
22 GND power_in Ground connection for the device.
23 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
24 OUT7B output Complementary LVDS or inverted CMOS output of the distribution section.
25 OUT7 output LVDS or CMOS clock output of the distribution section; LVDS up to 800 MHz or CMOS up to 250 MHz.
26 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
27 GND power_in Ground connection for the device.
28 OUT3B output Complementary LVPECL output, up to 1.2 GHz.
29 OUT3 output LVPECL clock output, up to 1.2 GHz.
30 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
31 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
32 GND power_in Ground connection for the device.
33 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
34 OUT2B output Complementary LVPECL output, up to 1.2 GHz.
35 OUT2 output LVPECL clock output, up to 1.2 GHz.
36 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
37 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
38 OUT6B output Complementary LVDS or inverted CMOS output; OUT6 includes a delay block.
39 OUT6 output LVDS or CMOS output with a delay block; LVDS up to 800 MHz or CMOS up to 250 MHz.
40 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
41 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
42 OUT5B output Complementary LVDS or inverted CMOS output; OUT5 includes a delay block.
43 OUT5 output LVDS or CMOS output with a delay block; LVDS up to 800 MHz or CMOS up to 250 MHz.
44 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
45 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
46 OUT4B output Complementary LVDS or inverted CMOS output.
47 OUT4 output LVDS or CMOS output; LVDS up to 800 MHz or CMOS up to 250 MHz.
48 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
49 GND power_in Ground connection for the device.
50 GND power_in Ground connection for the device.
51 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
52 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
53 OUT1B output Complementary LVPECL output, up to 1.2 GHz.
54 OUT1 output LVPECL clock output, up to 1.2 GHz.
55 GND power_in Ground connection for the device.
56 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
57 OUT0B output Complementary LVPECL output, up to 1.2 GHz.
58 OUT0 output LVPECL clock output, up to 1.2 GHz.
59 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
60 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
61 RSET passive Current set resistor to ground, nominal value 4.12 kΩ.
62 GND power_in Ground connection for the device.
63 CPRSET passive Charge pump current set resistor to ground, nominal value 5.1 kΩ.
64 VS power_in Power supply pin VS, 3.3 V nominal, with VS less than or equal to VCPS.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category Interface ICs
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VS to GND VS -0.3 3.6 V VS to GND 17
VCP to GND VCP -0.3 5.8 V VCP to GND 17
VCP to VS VCP-VS -0.3 5.8 V VCP to VS 17
CLK1 to CLK1B CLK1-CLK1B -1.2 1.2 V CLK1 to CLK1B 17
CLK2 to CLK2B CLK2-CLK2B -1.2 1.2 V CLK2 to CLK2B 17
Junction Temperature TJ 150 °C 17
Storage Temperature TSTG -65 150 °C 17
Lead Temperature 300 °C 10 sec 17
Thermal Resistance, junction to ambient θJA 24 °C/W 64-lead LFCSP, 4-layer board, still air, JESD51-7 17
Ambient Temperature Range TA -40 85 °C Min and max over full VS and TA variation 4
Supply voltage tolerance VS -5 5 % VS = 3.3 V supply 53
Charge pump supply VCPS 5.5 V VS ≤ VCPS ≤ 5.5 V 4
Self-bias Voltage, REFIN 1.45 1.6 1.75 V Self-bias voltage of REFIN 4
Self-bias Voltage, REFINB 1.4 1.5 1.6 V Self-bias voltage of REFINB 4
Input Resistance, REFIN 4 4.9 5.8 kΩ Self-biased 4
Input Resistance, REFINB 4.5 5.4 6.3 kΩ Self-biased 4
Input Frequency, REFIN 0 250 MHz 4
CPRSET Range CPRSET 2.7 10 kΩ 4
Input Common-Mode Voltage, VCM (CLK2) VCM 1.5 1.6 1.7 V Self-biased, enables ac coupling 4
Input Common-Mode Range, VCMR (CLK2) VCMR 1.3 1.8 V With 200 mV p-p signal applied 4
Input Resistance (CLK2) 4 4.8 5.6 kΩ Self-biased 4
Input Frequency (CLK1, CLK2) 0 1.6 GHz 5
Input Common-Mode Voltage (CLK1, CLK2) VCM 1.5 1.6 1.7 V Self-biased; enables ac coupling 5
Input Common-Mode Range (CLK1, CLK2) VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled 5
Input Resistance (CLK1, CLK2) 4 4.8 5.6 kΩ Self-biased 5
LVPECL Output High Voltage VOH -1.22 -0.98 -0.93 V relative to VS Termination = 50 Ω to VS − 2 V 6
LVPECL Output Low Voltage VOL -2.1 -1.8 -1.67 V relative to VS Termination = 50 Ω to VS − 2 V 6
LVPECL Output Differential Voltage VOD 660 810 965 mV Termination = 50 Ω to VS − 2 V 6
LVDS Differential Output Voltage VOD 250 360 450 mV Termination = 100 Ω differential; default 6
LVDS Output Offset Voltage VOS 1.125 1.23 1.375 V Termination = 100 Ω differential; default 6
Propagation Delay, CLK-to-LVPECL OUT1, Divide = Bypass tPECL 335 490 635 ps Divide = Bypass 6
Propagation Delay, CLK-to-LVPECL OUT1, Divide = 2-32 tPECL 375 545 695 ps Divide = 2 − 32 6
Output Skew, OUT1 to OUT0 on same part tSKP -5 30 85 ps OUT1 to OUT0 on same part 6
Output Skew, OUT2 to OUT3 on same part tSKP 15 45 80 ps OUT2 to OUT3 on same part 6
Output Skew, All LVPECL OUTs on same part tSKP 90 130 180 ps All LVPECL OUTs on same part 6
Propagation Delay, CLK-to-LVDS OUT, Divide = Bypass tLVDS 0.99 1.33 1.59 ns Divide = Bypass; delay off on OUT5 and OUT6 7
Propagation Delay, CLK-to-LVDS OUT, Divide = 2-32 tLVDS 1.04 1.38 1.64 ns Divide = 2 − 32; delay off on OUT5 and OUT6 7
Propagation Delay, CLK-to-CMOS OUT, Divide = Bypass tCMOS 1.02 1.39 1.71 ns Divide = Bypass; delay off on OUT5 and OUT6 7
Propagation Delay, CLK-to-CMOS OUT, Divide = 2-32 tCMOS 1.07 1.44 1.76 ns Divide = 2 − 32; delay off on OUT5 and OUT6 7
Output Skew, LVPECL to LVDS on same part tSKP_V 0.74 0.92 1.14 ns Everything the same; different logic type 7
Output Skew, LVPECL to CMOS on same part tSKP_C 0.88 1.14 1.43 ns Everything the same; different logic type 7
Output Skew, LVDS to CMOS on same part tSKV_C 158 353 506 ps Everything the same; different logic type 7
Shortest Delay Range, Zero Scale 0.05 0.36 0.68 ns Register 0x36, Register 0x3A[5:1] = 00000b; Register 0x39[5:1] = 11111b 7
Shortest Delay Range, Full Scale 0.57 0.95 1.32 ns Register 0x36, Register 0x3A[5:1] = 11000b; Register 0x39[5:1] = 11111b 7
Longest Delay Range, Zero Scale 0.2 0.57 0.95 ns Register 0x36, Register 0x3A[5:1] = 00000b; Register 0x39[5:1] = 00000b 7
Longest Delay Range, Full Scale 7 8 9.2 ns Register 0x36, Register 0x3A[5:1] = 11000b; Register 0x39[5:1] = 00000b 7
CLK1, CLK2 Power-Down 10 15 25 mW 15
Divider Power Delta, DIV 2-32 to Bypass 23 27 33 mW For each divider 15
LVPECL Output Power-Down PD2, PD3 50 65 75 mW For each output; does not include dissipation in termination (PD2 only) 15
LVDS Output Power-Down 80 92 110 mW For each output 15
CMOS Output Power-Down (Static) 56 70 85 mW For each output; static (no clock) 15
CMOS Output Power-Down (Dynamic) 115 150 190 mW For each CMOS output, single-ended; clocking at 62 MHz with 5 pF load 15
CMOS Output Power-Down (Dynamic) 125 165 210 mW For each CMOS output, single-ended; clocking at 125 MHz with 5 pF load 15
Delay Block Bypass 20 24 60 mW Versus delay block operation at 1 ns fs with maximum delay, output clocking at 25 MHz 15
PLL Section Power-Down 5 15 40 mW 15

CAD (KiCad official)

  • Symbol: AD9510BCPZ
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad9510bcpz-etched.step / ad9510bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9510bcpz.step / ad9510bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (56 pp, sha256 875ae3254bce29f0, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF