component
SN74LV20APWR
Public Made by Adomby adom
Texas Instruments Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownSN74LV20APWR
Texas Instruments · Logic ICs · TSSOP-14
SN74LV20APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input 1A of the first 4-input NAND gate, contributing to Y = A • B • C • D in positive logic. |
| 2 | 1B | input | Input 1B of the first 4-input NAND gate, contributing to Y = A • B • C • D in positive logic. |
| 3 | NC | unconnected | Not internally connected. |
| 4 | 1C | input | Input 1C of the first 4-input NAND gate, contributing to Y = A • B • C • D in positive logic. |
| 5 | 1D | input | Input 1D of the first 4-input NAND gate, contributing to Y = A • B • C • D in positive logic. |
| 6 | 1Y | output | Output 1Y of the first NAND gate, which goes low only when all four inputs are high; Ioff circuitry disables it when the device is powered down. |
| 7 | GND | power_in | Ground pin. |
| 8 | 2Y | output | Output 2Y of the second NAND gate, which goes low only when all four inputs are high; Ioff circuitry disables it when the device is powered down. |
| 9 | 2A | input | Input 2A of the second 4-input NAND gate, contributing to Y = A • B • C • D in positive logic. |
| 10 | 2B | input | Input 2B of the second 4-input NAND gate, contributing to Y = A • B • C • D in positive logic. |
| 11 | NC | unconnected | Not internally connected. |
| 12 | 2C | input | Input 2C of the second 4-input NAND gate, contributing to Y = A • B • C • D in positive logic. |
| 13 | 2D | input | Input 2D of the second 4-input NAND gate, contributing to Y = A • B • C • D in positive logic. |
| 14 | VCC | power_in | Power supply pin; operates from 2 V to 5.5 V VCC and should be bypassed with a 0.1-μF capacitor close to the terminal. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| Input voltage range | VI | -0.5 | 7 | V | 4 | ||
| Output voltage range, high or low state | VO | -0.5 | V | applied in high or low state; max printed as VCC + 0.5 V | 4 | ||
| Output voltage range, power-off state | VO | -0.5 | 7 | V | applied in power-off state | 4 | |
| Input clamp current | IIK | -20 | mA | VI < 0 | 4 | ||
| Output clamp current | IOK | -50 | mA | VO < 0 | 4 | ||
| Continuous output current | IO | -25 | 25 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD human body model | V(ESD) | -2000 | 2000 | V | HBM, per ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD charged device model | V(ESD) | -1000 | 1000 | V | CDM, per JEDEC JESD22-C101 | 4 | |
| Supply voltage | VCC | 2 | 5.5 | V | 4 | ||
| High level input voltage | VIH | 1.5 | V | VCC = 2 V | 4 | ||
| Low level input voltage | VIL | 0.5 | V | VCC = 2 V | 4 | ||
| Input voltage | VI | 0 | 5.5 | V | 4 | ||
| Output voltage | VO | 0 | V | max printed as VCC | 4 | ||
| High level output current | IOH | -50 | µA | VCC = 2 V | 4 | ||
| High level output current | IOH | -2 | mA | VCC = 2.3 V to 2.7 V | 4 | ||
| High level output current | IOH | -6 | mA | VCC = 3 V to 3.6 V | 4 | ||
| High level output current | IOH | -12 | mA | VCC = 4.5 V to 5.5 V | 4 | ||
| Low level output current | IOL | 50 | µA | VCC = 2 V | 5 | ||
| Low level output current | IOL | 2 | mA | VCC = 2.3 V to 2.7 V | 5 | ||
| Low level output current | IOL | 6 | mA | VCC = 3 V to 3.6 V | 5 | ||
| Low level output current | IOL | 12 | mA | VCC = 4.5 V to 5.5 V | 5 | ||
| Input transition rise and fall rate | Δt/Δv | 200 | ns/V | VCC = 2.3 V to 2.7 V | 5 | ||
| Input transition rise and fall rate | Δt/Δv | 100 | ns/V | VCC = 3 V to 3.6 V | 5 | ||
| Input transition rise and fall rate | Δt/Δv | 20 | ns/V | VCC = 4.5 V to 5.5 V | 5 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | 5 | ||
| Junction-to-ambient thermal resistance, PW package | RθJA | 113 | °C/W | PW (TSSOP-14) package | 5 | ||
| High-level output voltage | VOH | 2 | V | IOH = -2 mA, VCC 2.3 V | 5 | ||
| High-level output voltage | VOH | 2.48 | V | IOH = -6 mA, VCC 3 V | 5 | ||
| High-level output voltage | VOH | 3.8 | V | IOH = -12 mA, VCC 4.5 V | 5 | ||
| Low-level output voltage | VOL | 0.1 | V | IOL = 50 µA, VCC 2 V to 5.5 V | 5 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = 2 mA, VCC 2.3 V | 5 | ||
| Low-level output voltage | VOL | 0.44 | V | IOL = 6 mA, VCC 3 V | 5 | ||
| Low-level output voltage | VOL | 0.55 | V | IOL = 12 mA, VCC 4.5 V | 5 | ||
| Input leakage current | II | -1 | 1 | µA | VI = 5.5 V or GND, VCC 0 to 5.5 V | 5 | |
| Supply current | ICC | 20 | µA | VI = VCC or GND, IO = 0, VCC 5.5 V | 5 | ||
| Off-state leakage current | Ioff | 5 | µA | VI or VO = 0 to 5.5 V, VCC 0 V | 5 | ||
| Input capacitance | Ci | 1.9 | pF | VI = VCC or GND, VCC 3.3 V | 5 | ||
| Propagation delay A, B, C or D to Y, VCC 2.5 V | tpd | 1 | 13.5 | ns | CL = 15 pF, VCC = 2.5 V ± 0.2 V | 5 | |
| Propagation delay A, B, C or D to Y, VCC 2.5 V | tpd | 1 | 18.5 | ns | CL = 50 pF, VCC = 2.5 V ± 0.2 V | 5 | |
| Propagation delay A, B, C or D to Y, VCC 3.3 V | tpd | 1 | 8 | ns | CL = 15 pF, VCC = 3.3 V ± 0.3 V | 6 | |
| Propagation delay A, B, C or D to Y, VCC 3.3 V | tpd | 1 | 11.5 | ns | CL = 50 pF, VCC = 3.3 V ± 0.3 V | 6 | |
| Propagation delay A, B, C or D to Y, VCC 5 V | tpd | 1 | 6 | ns | CL = 15 pF, VCC = 5 V ± 0.5 V | 6 | |
| Propagation delay A, B, C or D to Y, VCC 5 V | tpd | 1 | 8 | ns | CL = 50 pF, VCC = 5 V ± 0.5 V | 6 | |
| Quiet output, maximum dynamic VOL | VOL(P) | 0.2 | 0.8 | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 | |
| Quiet output, minimum dynamic VOL | VOL(V) | 0 | -0.8 | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 | |
| Quiet output, minimum dynamic VOH | VOH(V) | 3.2 | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 | ||
| High-level dynamic input voltage | VIH(D) | 2.31 | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 | ||
| Low-level dynamic input voltage | VIL(D) | 0.99 | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 | ||
| Power dissipation capacitance | Cpd | 20.5 | pF | CL = 50 pF, f = 10 MHz, VCC 3.3 V, TA = 25°C | 6 | ||
| Power dissipation capacitance | Cpd | 23.9 | pF | CL = 50 pF, f = 10 MHz, VCC 5 V, TA = 25°C | 6 |
CAD (KiCad official)
- Symbol:
SN74LV20APWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lv20apwr-etched.step/sn74lv20apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv20apwr.step/sn74lv20apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
3e6ebe8a87dd7951, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).