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DRV8935PPWPR

Public Made by Adom

by adom

Texas Instruments Gate Drive ICs, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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DRV8935PPWPR

Texas Instruments · Gate Drive ICs · HTSSOP-28-EP

DRV8935PPWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCP power_out Charge-pump output; connect a X7R 0.22µF 16V ceramic capacitor between VCP and VM.
2 VM power_in Motor supply input with a recommended range of 4.5 V to 33 V; bypass each VM pin with a 0.01µF ceramic capacitor rated VM plus a bulk capacitor to PGND.
3 PGND power_in Power ground shared by all half-bridges; connect to system ground.
4 OUT1 output Half-bridge 1 output; continuous phase-node voltage is limited to -1 V to VM + 1 V.
5 OUT1 output Half-bridge 1 output; continuous phase-node voltage is limited to -1 V to VM + 1 V.
6 OUT2 output Half-bridge 2 output; continuous phase-node voltage is limited to -1 V to VM + 1 V.
7 OUT2 output Half-bridge 2 output; continuous phase-node voltage is limited to -1 V to VM + 1 V.
8 OUT4 output Half-bridge 4 output; continuous phase-node voltage is limited to -1 V to VM + 1 V.
9 OUT4 output Half-bridge 4 output; continuous phase-node voltage is limited to -1 V to VM + 1 V.
10 OUT3 output Half-bridge 3 output; continuous phase-node voltage is limited to -1 V to VM + 1 V.
11 OUT3 output Half-bridge 3 output; continuous phase-node voltage is limited to -1 V to VM + 1 V.
12 PGND power_in Power ground shared by all half-bridges; connect to system ground.
13 VM power_in Motor supply input with a recommended range of 4.5 V to 33 V; bypass with a 0.01µF ceramic capacitor rated VM plus a bulk capacitor to PGND.
14 GND power_in Device ground; connect to system ground.
15 DVDD power_out Internal logic regulator output, nominally 5 V and able to supply up to 2 mA; bypass to GND with a X7R 0.47µF to 1µF ceramic capacitor rated 6.3 V or 10 V.
16 nFAULT output Open-drain fault output pulled low during a fault; requires an external pull-up to 5 V, 3.3 V or 1.8 V and sinks up to 10 mA.
17 VREF34 input Reference voltage input setting the current trip level for half-bridges 3 and 4, with ITRIP = VREF / 1.32 V/A and VREF from 0.05 V to 3.3 V.
18 VREF12 input Reference voltage input setting the current trip level for half-bridges 1 and 2, with ITRIP = VREF / 1.32 V/A and VREF from 0.05 V to 3.3 V.
19 TOFF input Four-level input that sets the PWM current-chopping off time to 7, 16, 24 or 32 µs.
20 NC unconnected No connection.
21 NC unconnected No connection.
22 IN4 input PWM logic input controlling the state of half-bridge 4, with an internal pull-down and a 0 V to 5.5 V input range.
23 IN3 input PWM logic input controlling the state of half-bridge 3, with an internal pull-down and a 0 V to 5.5 V input range.
24 IN2 input PWM logic input controlling the state of half-bridge 2, with an internal pull-down and a 0 V to 5.5 V input range.
25 IN1 input PWM logic input controlling the state of half-bridge 1, with an internal pull-down and a 0 V to 5.5 V input range.
26 nSLEEP input Sleep-mode input; logic high enables the device and logic low puts it into low-power sleep mode, with a 0 V to VM input range and an internal pull-down.
27 CPL passive Charge-pump negative switch node; connect a X7R 0.022µF ceramic capacitor rated VM between CPH and CPL.
28 CPH passive Charge-pump switch node; connect a X7R 0.022µF ceramic capacitor rated VM between CPH and CPL.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28-EP
Category Power Supply Chip
Pins 29

CAD (KiCad official)

  • Symbol: DRV8935PPWPR
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: drv8935ppwpr-etched.step / drv8935ppwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8935ppwpr.step / drv8935ppwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 6967c04befb26dbd, retrieved 2026-10-28, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF