component
AW9968DNR
Public Made by Adomby adom
AWINIC(Shanghai Awinic Tech) LED Drivers, DFN-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAW9968DNR
AWINIC(Shanghai Awinic Tech) · LED Drivers · DFN-6-EP(2x2)
AW9968DNR from AWINIC(Shanghai Awinic Tech), in a DFN-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback pin: RSET is connected from FB to GND, and the loop regulates FB to a 200mV typical reference in backlight mode. |
| 2 | STROBE | input | Strobe signal input that synchronizes the flash pulse to image capture; the AW9968 exits flash mode if STROBE stays high for more than 350ms. |
| 3 | GND | power_in | Ground. |
| 4 | SW | output | Switching node of the boost converter; the open-LED overvoltage threshold is measured on this pin, 38V typical with a 36V to 40V range. |
| 5 | CTRL | input | Enable pin that also accepts PWM digital dimming; a logic low for more than 2.5ms shuts the driver down. |
| 6 | VIN | power_in | Power input with an input voltage range of 2.7V to 5.5V. |
| 7 | GND | power_in | Exposed pad that should be soldered to the PCB and connected to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AWINIC(Shanghai Awinic Tech) |
| Package | DFN-6-EP(2x2) |
| Category | Nixie Tube Driver/LED Driver |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VIN | VIN | -0.3 | 6 | V | With respect to network ground (NOTE 2) | 5 | |
| Voltage on FB, STROBE, CTRL | -0.3 | 6 | V | With respect to network ground (NOTE 2) | 5 | ||
| Voltage on SW | -0.3 | 40 | V | With respect to network ground (NOTE 2) | 5 | ||
| Junction-to-ambient thermal resistance | θJA | 120 | °C/W | 5 | |||
| Operating free-air temperature range | -40 | 85 | °C | 5 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 5 | ||
| Lead temperature (soldering) | 260 | °C | Soldering 10 seconds | 5 | |||
| ESD HBM all pins | -2 | 2 | kV | Human body model, all pins (NOTE 4) | 5 | ||
| ESD CDM all pins | -1.5 | 1.5 | kV | Charge device model, all pins (NOTE 5) | 5 | ||
| Latch-up +IT | +IT | 200 | mA | JEDEC latch-up current maximum rating | 5 | ||
| Latch-up -IT | -IT | -200 | mA | JEDEC latch-up current maximum rating | 5 | ||
| Input voltage range | VIN | 2.7 | 5.5 | V | 7 | ||
| Under-voltage lockout threshold | VUVLO | 2.2 | 2.39 | V | VIN falling | 7 | |
| Shutdown current | ISD | 0.1 | 1 | A | VCTRL = GND, VIN=4.2V | 7 | |
| Frequency of PWM dimming | fPWM | 10 | 100 | kHz | 7 | ||
| PWM dimming duty cycle | DPWM | 0.3 | 100 | % | 7 | ||
| Voltage feedback regulation voltage in Backlight Mode | VREF_BL | 194 | 200 | 205 | mV | PWM duty cycle = 100% | 7 |
| Voltage feedback regulation voltage in Flash Mode | VREF_FL | 975 | 1000 | 1025 | mV | PWM duty cycle = 100% | 7 |
| Voltage feedback regulation voltage under brightness control in Backlight Mode | VREF_PWM | 1.575 | 2.25 | 2.925 | mV | PWM duty cycle = 1% | 7 |
| Voltage feedback regulation voltage under brightness control in Backlight Mode | VREF_PWM | 0.5 | 1.25 | 2 | mV | PWM duty cycle = 0.5% | 7 |
| Voltage feedback input bias current | IFB | 0.1 | 1 | A | 7 | ||
| Oscillator frequency | fS | 800 | 1100 | 1400 | kHz | 7 | |
| Maximum duty cycle | DMAX | 90 | 93 | % | 7 | ||
| N-channel MOSFET current limit in Backlight Mode | ILIM_BL | 1.5 | 2 | 2.5 | A | 7 | |
| N-channel MOSFET current limit in Flash Mode | ILIM_FL | 2.25 | 3 | 3.75 | A | 7 | |
| Open LED overvoltage protection threshold | VOVP | 36 | 38 | 40 | V | Measured on the SW pin | 7 |
| CTRL logic high voltage | VCTRL_H | 1.4 | V | VIN = 2.7V to 5.5V | 8 | ||
| CTRL logic low voltage | VCTRL_L | 0.4 | V | VIN = 2.7V to 5.5V | 8 | ||
| STROBE logic high voltage | VSTROBE_H | 1.4 | V | VIN = 2.7V to 5.5V | 8 | ||
| STROBE logic low voltage | VSTROBE_L | 0.4 | V | VIN = 2.7V to 5.5V | 8 | ||
| Under-voltage lockout hysteresis | VHYS | 100 | mV | 7 | |||
| Operating quiescent current | IQ | 250 | A | VFB = 1V | 7 | ||
| Minimum on pulse width | tMIN_ON | 50 | ns | 7 | |||
| VREF_PWM at 0.3% duty | VREF_PWM | 0.6 | mV | PWM duty cycle = 0.3% | 7 | ||
| N-channel MOSFET on-resistance | RDS(on) | 0.25 | Ω | VIN = 3.6V | 7 | ||
| N-channel MOSFET on-resistance | RDS(on) | 0.5 | Ω | VIN = 3.0V | 7 | ||
| VREF filter time constant | tREF | 480 | s | 7 | |||
| CTRL pull down resistor | RCTRL | 600 | kΩ | 8 | |||
| CTRL pulse width to shutdown | tOFF | 2.5 | ms | CTRL high to low | 8 | ||
| STROBE pull down resistor | RSTROBE | 200 | kΩ | 8 | |||
| Flash mode timer | tFL_OFF | 350 | ms | 8 | |||
| Thermal shutdown threshold | TOTP | 165 | °C | 8 | |||
| Thermal shutdown threshold hysteresis | THYS | 15 | °C | 8 |
CAD (KiCad official)
- Symbol:
AW9968DNR - Footprint:
Package_DFN_QFN:DFN-6-1EP_2x2mm_P0.65mm_EP1x1.6mm - 3D model: DFN-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
aw9968dnr-etched.step/aw9968dnr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aw9968dnr.step/aw9968dnr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: AWINIC(Shanghai Awinic Tech) datasheet (22 pp, sha256
0c1343ca428bcad0, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).