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CD4067TA24.TB

Public Made by Adom

by adom

Wuxi I-core Elec Flip Flops, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4067TA24.TB

Wuxi I-core Elec · Flip Flops · TSSOP-24

CD4067TA24.TB from Wuxi I-core Elec, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Z bidirectional Common input/output of the sixteen bidirectional analog switches, swinging between VSS and VDD.
2 Y7 bidirectional Independent analog input/output connected to Z when address A3-A0 = 0111 and E is LOW.
3 Y6 bidirectional Independent analog input/output connected to Z when address A3-A0 = 0110 and E is LOW.
4 Y5 bidirectional Independent analog input/output connected to Z when address A3-A0 = 0101 and E is LOW.
5 Y4 bidirectional Independent analog input/output connected to Z when address A3-A0 = 0100 and E is LOW.
6 Y3 bidirectional Independent analog input/output connected to Z when address A3-A0 = 0011 and E is LOW.
7 Y2 bidirectional Independent analog input/output connected to Z when address A3-A0 = 0010 and E is LOW.
8 Y1 bidirectional Independent analog input/output connected to Z when address A3-A0 = 0001 and E is LOW.
9 Y0 bidirectional Independent analog input/output connected to Z when address A3-A0 = 0000 and E is LOW.
10 A0 input Address input bit 0 (LSB) selecting one of the sixteen channels.
11 A1 input Address input bit 1 selecting one of the sixteen channels.
12 VSS power_in Ground (0V) supply reference and negative limit for the analog signal swing.
13 A3 input Address input bit 3 (MSB) selecting one of the sixteen channels.
14 A2 input Address input bit 2 selecting one of the sixteen channels.
15 E input Active-LOW enable input; when HIGH all switches are in the high-impedance OFF-state regardless of A0-A3.
16 Y15 bidirectional Independent analog input/output connected to Z when address A3-A0 = 1111 and E is LOW.
17 Y14 bidirectional Independent analog input/output connected to Z when address A3-A0 = 1110 and E is LOW.
18 Y13 bidirectional Independent analog input/output connected to Z when address A3-A0 = 1101 and E is LOW.
19 Y12 bidirectional Independent analog input/output connected to Z when address A3-A0 = 1100 and E is LOW.
20 Y11 bidirectional Independent analog input/output connected to Z when address A3-A0 = 1011 and E is LOW.
21 Y10 bidirectional Independent analog input/output connected to Z when address A3-A0 = 1010 and E is LOW.
22 Y9 bidirectional Independent analog input/output connected to Z when address A3-A0 = 1001 and E is LOW.
23 Y8 bidirectional Independent analog input/output connected to Z when address A3-A0 = 1000 and E is LOW.
24 VDD power_in Supply voltage, 3V to 9V recommended (absolute maximum +12V), and positive limit for the analog signal swing.

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package TSSOP-24
Category Logic ICs
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 12 V 7
Input clamping current IIK 10 mA VI<0.5V or VI>VDD+0.5V; printed ±10 7
Switch current I 10 mA printed ±10 7
Input voltage VI -0.5 V all inputs; max VDD+0.5 7
Storage temperature Tstg -65 150 ℃ 7
Total power dissipation Ptot 500 mW (T)SSOP24 derates 5.5mW/K above 60℃ 7
Device dissipation P 100 mW per output transistor 7
Soldering temperature TL 250 ℃ 10s 7
Supply voltage VDD 3 5 9 V 7
Ambient temperature Tamb -40 105 ℃ in free air 7
Input voltage VI 0 V max VDD 7
Multiplexer switch input current capability 25 mA 7
Output load resistance 100 Ω 7
LOW-level input voltage VIL 1.5 V /IO/<1uA; VDD=5V, VO=0.5V or 4.5V; Tamb=25℃ 8
LOW-level input voltage VIL 3 V /IO/<1uA; VDD=9V, VO=1.0V or 9V; Tamb=25℃ 8
HIGH-level input voltage VIH 3.5 V /IO/<1uA; VDD=5V, VO=0.5V or 4.5V; Tamb=25℃ 8
HIGH-level input voltage VIH 7 V /IO/<1uA; VDD=9V, VO=1.0V or 9V; Tamb=25℃ 8
OFF-state leakage current IS(OFF) -100 100 nA VSS=0V; VDD=9V; Tamb=25℃; typ printed ±0.1 8
Supply current IDD 0.04 5 uA all valid input combinations; IO=0A; VDD=5V; Tamb=25℃ 8
Supply current IDD 0.04 10 uA all valid input combinations; IO=0A; VDD=9V; Tamb=25℃ 8
Input capacitance CI 5 7.5 pF any address or inhibit input 8
ON resistance RON 470 1050 Ω VSS≤Vis≤VDD; VDD=5V; Tamb=25℃ 8
ON resistance RON 180 400 Ω VSS≤Vis≤VDD; VDD=9V; Tamb=25℃ 8
Change in on-state resistance between channels △RON 15 Ω VDD=5V 8
Change in on-state resistance between channels △RON 10 Ω VDD=9V 8
Input leakage current II -0.1 0.1 uA VI=0V or 9V, VDD=9V; Tamb=-40℃; printed ±0.1 8
Input leakage current II -1 1 uA VI=0V or 9V, VDD=9V; Tamb=+85℃ and +105℃; printed ±1 8
OFF-state leakage current IS(OFF) -1000 1000 nA VSS=0V; VDD=9V; Tamb=+85℃ and +105℃; printed ±1000 8
Supply current IDD 5 uA VDD=5V; IO=0A; Tamb=-40℃ 8
Supply current IDD 150 uA VDD=5V; IO=0A; Tamb=+85℃ and +105℃ 8
Supply current IDD 10 uA VDD=9V; IO=0A; Tamb=-40℃ 8
Supply current IDD 300 uA VDD=9V; IO=0A; Tamb=+85℃ and +105℃ 8
ON resistance RON 850 Ω VSS≤Vis≤VDD; VDD=5V; Tamb=-40℃ 8
ON resistance RON 1200 Ω VSS≤Vis≤VDD; VDD=5V; Tamb=+85℃ 8
ON resistance RON 1300 Ω VSS≤Vis≤VDD; VDD=5V; Tamb=+105℃ 8
ON resistance RON 330 Ω VSS≤Vis≤VDD; VDD=9V; Tamb=-40℃ 8
ON resistance RON 520 Ω VSS≤Vis≤VDD; VDD=9V; Tamb=+85℃ 8
ON resistance RON 550 Ω VSS≤Vis≤VDD; VDD=9V; Tamb=+105℃ 8
HIGH to LOW propagation delay time tPHL 30 60 ns Yn, Z to Z, Yn; VDD=5V 9
HIGH to LOW propagation delay time tPHL 15 30 ns Yn, Z to Z, Yn; VDD=9V 9
LOW to HIGH propagation delay tPLH 30 60 ns Yn, Z to Z, Yn; VDD=5V 9
LOW to HIGH propagation delay tPLH 15 30 ns Yn, Z to Z, Yn; VDD=9V 9
HIGH to OFF-state propagation delay tPHZ 325 650 ns E to Yn, Z; VDD=5V 9
HIGH to OFF-state propagation delay tPHZ 135 270 ns E to Yn, Z; VDD=9V 9
LOW to OFF-state propagation delay tPLZ 325 650 ns E to Yn, Z; VDD=5V 9
LOW to OFF-state propagation delay tPLZ 135 270 ns E to Yn, Z; VDD=9V 9
OFF-state to HIGH propagation delay tPZH 220 440 ns E to Yn, Z; VDD=5V 9
OFF-state to HIGH propagation delay tPZH 90 180 ns E to Yn, Z; VDD=9V 9
OFF-state to LOW propagation delay tPZL 220 440 ns E to Yn, Z; VDD=5V 9
OFF-state to LOW propagation delay tPZL 90 180 ns E to Yn, Z; VDD=9V 9
-3dB frequency response, Vos at Z f(-3dB) 14 MHz Vis=5V; VDD=9V; RL=1kΩ 9
-3dB frequency response, Vos at any channel f(-3dB) 60 MHz Vis=5V; VDD=9V; RL=1kΩ 9
Total harmonic distortion THD 0.3 % fis=1kHz sine wave; Vis=2V; VDD=5V; RL=10kΩ 9
Total harmonic distortion THD 0.2 % fis=1kHz sine wave; Vis=3V; VDD=9V; RL=10kΩ 9
Crosstalk voltage Vct 75 mV VDD=9V; RL=10kΩ; VC=VDD-VSS (square wave) 9

CAD (KiCad official)

  • Symbol: CD4067TA24.TB
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: cd4067ta24-tb-etched.step / cd4067ta24-tb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4067ta24-tb.step / cd4067ta24-tb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (15 pp, sha256 c8789a686f3cd801, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF