Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83822IFRHBT

Texas Instruments · Ethernet Transceivers · VQFN-32-EP(5x5)

DP83822IFRHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RX_D3/GPIO3	bidirectional	MII/RGMII receive data bit 3 (RX_D3 is required in those modes), also configurable as an LED or GPIO3 via registers; strap pin for PHY_AD4/AN_EN with weak internal pull-down.
2	TX_CLK	bidirectional	MII transmit clock output (25MHz at 100Mbps, 2.5MHz at 10Mbps), unused in RMII; becomes an input with internal pull-down in RGMII (25MHz/2.5MHz) after reset, driven low as an output during reset.
3	TX_EN/TX_CTRL	input	Transmit enable (active high, MII/RMII) or combined RGMII transmit control, with internal pull-down.
4	TX_D0	input	Transmit data bit 0 from the MAC, synchronous to TX_CLK (MII/RGMII) or the reference clock (RMII), with internal pull-down.
5	TX_D1	input	Transmit data bit 1 from the MAC, synchronous to TX_CLK (MII/RGMII) or the reference clock (RMII), with internal pull-down.
6	TX_D2	input	Transmit data bit 2 from the MAC (MII/RGMII), synchronous to TX_CLK, with internal pull-down.
7	TX_D3	input	Transmit data bit 3 from the MAC (MII/RGMII), synchronous to TX_CLK, with internal pull-down.
8	INT/PWDN_N	bidirectional	Open-drain interrupt output or active-low power-down input (default is power-down), with weak internal pull-up; some applications need an external pull-up.
9	RD_M	input	Differential receive input (PMD) automatically configured for 10BASE-Te, 100BASE-TX or 100BASE-FX signaling.
10	RD_P	input	Differential receive input (PMD) automatically configured for 10BASE-Te, 100BASE-TX or 100BASE-FX signaling.
11	TD_M	output	Differential transmit output (PMD) automatically configured for 10BASE-Te, 100BASE-TX or 100BASE-FX signaling.
12	TD_P	output	Differential transmit output (PMD) automatically configured for 10BASE-Te, 100BASE-TX or 100BASE-FX signaling.
13	NC	unconnected	No connect; leave floating.
14	AVD	power_in	Analog supply, 3.3V or 1.8V.
15	NC	unconnected	No connect; leave floating.
16	RBIAS	passive	Bias resistor connection; a 4.87kΩ ±1% resistor must be connected from RBIAS to GND.
17	LED_0	output	Link LED output (default) or link plus TX/RX activity indication; strap pin with weak internal pull-up.
18	RESET_N	input	Active-low reset input with internal pull-up that reinitializes all internal registers; hold low for at least 10μs.
19	MDIO	bidirectional	Bidirectional management data I/O; requires a 2.2kΩ pull-up resistor.
20	MDC	input	Management data clock for MDIO with internal pull-down; maximum 25MHz, no minimum rate.
21	VDDIO	power_in	I/O supply, 3.3V, 2.5V or 1.8V.
22	XO	output	Crystal output for the reference clock; must be left floating when a CMOS oscillator drives XI.
23	XI	input	Crystal/oscillator input: 25MHz ±100ppm for MII/RGMII/RMII master, or 50MHz ±100ppm CMOS oscillator for RMII slave.
24	LED_1/GPIO1	bidirectional	Speed LED (tri-state by default), GPIO1, or 100BASE-FX signal detect input (VDDIO level); strap pin with internal pull-down, may float if unused.
25	RX_CLK	output	MII/RGMII receive clock (25MHz at 100Mbps, 2.5MHz at 10Mbps) derived from the received data stream; unused in RMII.
26	RX_DV/RX_CTRL	output	Receive data valid (MII/RMII) or combined RGMII receive control; strap pin with internal pull-down.
27	CRS/CRS_DV	output	Carrier sense (MII) or carrier sense/receive data valid (RMII), unused in RGMII; strap pin with internal pull-up.
28	RX_ER	output	Receive error indication in MII/RMII modes, unused in RGMII; strap pin with internal pull-up.
29	COL/GPIO2	bidirectional	MII collision detect (low in full duplex), or LED/GPIO2 via registers; strap pin for PHY_AD0/FX_EN with internal pull-up, unused in RMII.
30	RX_D0	output	Receive data bit 0 synchronous to RX_CLK; strap pin for PHY_AD1/AN_1 with internal pull-down.
31	RX_D1	output	Receive data bit 1 synchronous to RX_CLK; strap pin for PHY_AD2/EEE_EN with internal pull-down.
32	RX_D2	output	Receive data bit 2 (MII/RGMII) synchronous to RX_CLK; strap pin for PHY_AD3/FLD_EN with internal pull-down.
33	GND	power_in	Ground; exposed thermal pad of the VQFN package.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32-EP(5x5)
Category	Interface
Pins	33

CAD (KiCad official)

Symbol: DP83822IFRHBT
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: dp83822ifrhbt-etched.step / dp83822ifrhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83822ifrhbt.step / dp83822ifrhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (130 pp, sha256 a83a75e6aa9a4729, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF