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DRV8234RTER

Public Made by Adom

by adom

Texas Instruments Brushed DC Motor Drivers, QFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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DRV8234RTER

Texas Instruments · Brushed DC Motor Drivers · QFN-16(3x3)

DRV8234RTER from Texas Instruments, in a QFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IPROPI output Analog current output proportional to load current; connect a resistor from IPROPI to ground, with IIPROPI limited to 0 to 3 mA.
2 RSVD unconnected Reserved pin; leave this pin unconnected.
3 RC_OUT output Open-drain ripple counting output, programmable over I2C as a pulse train or logic level; pull up to a 5-V or 3.3-V supply with VOD up to 5.5 V and IOD up to 5 mA.
4 nFAULT output Open-drain fault indicator, pulled low during a fault condition; requires an external pullup resistor, with VOD up to 5.5 V and IOD up to 5 mA.
5 VM power_in Motor power supply rated 4.5 V to 38 V; bypass to GND with a 0.1-µF ceramic capacitor plus sufficient bulk capacitance rated for VM.
6 OUT1 output H-bridge output connected directly to the motor, with peak output current up to 3.7 A.
7 GND power_in Device ground; connect to system ground.
8 OUT2 output H-bridge output connected directly to the motor, with peak output current up to 3.7 A.
9 A1 input I2C base address select pin, tri-level input.
10 A0 input I2C base address select pin, tri-level input.
11 nSLEEP input Sleep mode input; logic high enables the device and logic low enters low-power sleep mode, with logic input range 0 to 5.5 V and an internal pulldown resistor.
12 PH/IN2 input Controls the H-bridge output with an internal pulldown; logic input range 0 to 5.5 V.
13 EN/IN1 input Controls the H-bridge output with an internal pulldown; logic input range 0 to 5.5 V.
14 SDA bidirectional I2C data signal; requires a pullup resistor.
15 SCL input I2C clock signal.
16 VREF power_in Analog input that sets the current regulation and stall detection level; recommended VREF range 0 to 3.3 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-16(3x3)
Category Motor Driver ICs
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply pin voltage VM -0.5 40 V 5
Power supply transient voltage ramp VM 0 2 V/µs 5
Logic pin voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP -0.3 5.75 V 5
Open-drain output pin voltage nFAULT, RC_OUT -0.3 5.75 V 5
Proportional current output pin voltage IPROPI -0.3 5.75 V VM ≥ 5.45 V 5
Proportional current output pin voltage IPROPI -0.3 V VM < 5.45 V 5
Reference input pin voltage VREF 0.3 5.75 V 5
Ambient temperature TA -40 125 °C 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Power supply voltage VM VVM 4.5 38 V 5
Logic input voltage IN1, IN2, A1, A0, SDA, SCL, nSLEEP VIN 0 5.5 V 5
PWM frequency INx fPWM 0 200 kHz 5
Open drain pullup voltage nFAULT, RC_OUT VOD 0 5.5 V 5
Open drain output current nFAULT, RC_OUT IOD 0 5 mA 5
Peak output current OUTx IOUT 0 3.7 A 5
Current sense output current IPROPI IIPROPI 0 3 mA 5
Current limit reference voltage VREF VVREF 0 3.3 V 5
Operating ambient temperature TA -40 125 °C 5
Operating junction temperature TJ -40 150 °C 5
VM sleep mode current IVMQ 0.1 1 µA nSLEEP = 0 V, VVM = 24 V, TJ = 27°C 6
VM active mode current IVM 3.5 4 mA nSLEEP = 3.3 V, IN1 = 3.3 V, IN2 = 0 V, VVM = 24 V 6
Turnon time tWAKE 410 µs nSLEEP = 1 to I2C ready 6
Input logic low voltage VIL 0 0.5 V 6
Input logic high voltage VIH 1.5 5.5 V 6
Input logic low current IIL -1 1 µA VI = 0 V 6
Input logic high current IIH 33 100 µA VI = 5 V 6
Tri-level input logic low voltage VTIL 0 0.6 V 6
Tri-level input Hi-Z voltage VTIHZ 1.8 2 2.2 V 6
Tri-level input logic high voltage VTIH 2.7 5.5 V 6
Output logic low voltage VOL 0.3 V IOD = 5 mA 6
Output logic high current IOZ -1 1 µA VOD = 3.3 V 6
RC_OUT pulse width tPW_RC 30 50 70 µs 6
nFAULT low pulse width tPW_nFAULT 30 50 70 µs RC Count overflow, RC_REP = 11b 6
SDA capacitive load for each bus line CB 400 pF 6
High-side MOSFET on resistance RDS(ON)_HS 300 360 mΩ IOUTx = 1 A; TJ = 25 °C 6
High-side MOSFET on resistance RDS(ON)_HS 450 540 mΩ IOUTx = 1 A; TJ = 125 °C 6
High-side MOSFET on resistance RDS(ON)_HS 500 600 mΩ IOUTx = 1 A; TJ = 150 °C 6
Low-side MOSFET on resistance RDS(ON)_LS 300 360 mΩ IOUTx = -1 A; TJ = 25 °C 6
Low-side MOSFET on resistance RDS(ON)_LS 450 540 mΩ IOUTx = -1 A; TJ = 125 °C 7
Low-side MOSFET on resistance RDS(ON)_LS 500 600 mΩ IOUTx = -1 A; TJ = 150 °C 7
Internal reference voltage VREF_INT 2.88 3 3.12 V INT_VREF = 1b 7
Current mirror total error AERR -10 10 % IOUT = 0.1 A, VVM ≥ 5.5 V 7
Current mirror total error AERR -7 7 % 0.15 A ≤ IOUT < 0.5 A, VVM ≥ 5.5 V 7
Current mirror total error AERR -5 5 % IOUT ≥ 0.5 A, VVM ≥ 5.5 V 7
Inrush time blanking for stall detection tINRUSH 5 ms 7
Line regulation ΔVLINE -2 2 % 5.5 V ≤ VVM ≤ 38 V, VOUT = 5 V, IOUT = 2 A 7
Load regulation ΔVLOAD -1 1 % VVM = 24 V, VOUT = 5 V, IOUT = 100 mA to 2 A 7
VM supply undervoltage lockout rising threshold VUVLO_VM 4.15 4.3 4.45 V Supply rising 7
VM supply undervoltage lockout falling threshold VUVLO_VM 4.05 4.2 4.35 V Supply falling 7
Thermal shutdown temperature TTSD 150 175 °C 7
Junction-to-ambient thermal resistance RθJA 47.8 °C/W 6
Junction-to-case (top) thermal resistance RθJC(top) 48.2 °C/W 6
Junction-to-board thermal resistance RθJB 22.4 °C/W 6
Junction-to-top characterization parameter ΨJT 1.1 °C/W 6
Junction-to-board characterization parameter ΨJB 22.4 °C/W 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 8.6 °C/W 6
Current scaling factor AIPROPI 1500 µA/A 7
Overcurrent protection trip point IOCP 3.7 A 7
Overvoltage protection threshold VOVP_TH 200 mV VOUT - VVM 7

CAD (KiCad official)

  • Symbol: DRV8234RTER
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: QFN-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: drv8234rter-etched.step / drv8234rter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8234rter.step / drv8234rter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (90 pp, sha256 a5714cc3fb790284, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF