component
TPS53681RSBT
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, QFN-40-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPS53681RSBT
Texas Instruments · AC-DC Controllers And Regulators · QFN-40-EP(5x5)
TPS53681RSBT from Texas Instruments, in a QFN-40-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BPWM1 | output | PWM signal for phase 1 of channel B. |
| 2 | BPWM2 | output | PWM signal for phase 2 of channel B. |
| 3 | APWM6/BPWM3 | output | PWM signal for phase 6 of channel A, or phase 3 of channel B, selected by the NVM option. |
| 4 | APWM5 | output | PWM signal for phase 5 of channel A. |
| 5 | APWM4 | output | PWM signal for phase 4 of channel A. |
| 6 | APWM3 | output | PWM signal for phase 3 of channel A. |
| 7 | APWM2 | output | PWM signal for phase 2 of channel A. |
| 8 | APWM1 | output | PWM signal for phase 1 of channel A. |
| 9 | SMB_DIO | bidirectional | SMBus or I2C bidirectional serial data interface, open drain. |
| 10 | SMB_CLK | input | SMBus or I2C serial clock interface, open drain. |
| 11 | SMB_ALERT | bidirectional | SMBus or I2C bidirectional ALERT pin, open drain. |
| 12 | AVR_RDY | output | Open-drain power-good output for channel A that requires an external pull-up resistor and is pulled low when a shutdown fault occurs. |
| 13 | AVR_EN | input | Active-high enable input for channel A; asserting it activates channel A, and recycling BVR_EN clears channel A faults. |
| 14 | VR_HOT | output | Active-low external temperature indicator output. |
| 15 | RESET | bidirectional | Resets the output voltage to the BOOT voltage when the ASIC signals an out-of-range condition during AVS operation. |
| 16 | BVR_RDY | output | Open-drain power-good output for channel B that requires an external pull-up resistor and is pulled low when a shutdown fault occurs. |
| 17 | GND | power_in | Connect to GND. |
| 18 | GND | power_in | Connect to GND. |
| 19 | NC | unconnected | No connection. |
| 20 | BVR_EN | input | Active-high enable input for channel B; asserting it activates channel B, and recycling BVR_EN clears channel B faults. |
| 21 | AVSP | input | Positive input of the remote voltage sense for channel A. |
| 22 | AVSN | input | Negative input of the remote voltage sense for channel A. |
| 23 | ACSP1 | input | Current sense input for channel A, connected to the IOUT pin of TI smart power stages; tie to V3P3 per Table 1 to disable the phase. |
| 24 | ACSP2 | input | Current sense input for channel A, connected to the IOUT pin of TI smart power stages; tie to V3P3 per Table 1 to disable the phase. |
| 25 | ACSP3 | input | Current sense input for channel A, connected to the IOUT pin of TI smart power stages; tie to V3P3 per Table 1 to disable the phase. |
| 26 | ACSP4 | input | Current sense input for channel A, connected to the IOUT pin of TI smart power stages; tie to V3P3 per Table 1 to disable the phase. |
| 27 | ACSP5 | input | Current sense input for channel A, connected to the IOUT pin of TI smart power stages; tie to V3P3 per Table 1 to disable the phase. |
| 28 | ACSP6/BCSP3 | input | Current sense input for channel A or channel B based on NVM option, connected to the IOUT pin of smart power stages; tie to the 3.3-V supply to disable the phase. |
| 29 | BCSP2 | input | Current sense input for channel B, connected to the IOUT pins of TI smart power stages; tie to V3P3 per Table 1 to disable the phase. |
| 30 | BVSP | input | Positive input of the remote voltage sense for channel B; connect to GND if channel B is not used. |
| 31 | BVSN | input | Negative input of the remote voltage sense for channel B; connect to GND if channel B is not used. |
| 32 | BCSP1 | input | Current sense input for channel B, connected to the IOUT pins of TI smart power stages; connect to GND if channel B is not used. |
| 33 | VR_FAULT | output | Open-drain VR fault indicator that goes LOW on high-side FET short, over-voltage, over-temperature or input over-current and latches the controller off. |
| 34 | ADDR | input | Voltage divider to VREF and GND whose level sets the 7-bit PMBus address via ADC, latched at 3.3-V power-up. |
| 35 | BTSEN | output | Connects to the TAO pin of channel B TI smart power stages to sense the highest power-stage temperature and the built-in fault signal. |
| 36 | ATSEN | output | Connects to the TAO pin of channel A TI smart power stages to sense the highest power-stage temperature and the built-in fault signal. |
| 37 | CSPIN | input | Positive terminal of the input current sensing shunt; when input current sensing is not used, short to VIN_CSNIN and connect to the converter input voltage. |
| 38 | VIN_CSNIN | power_in | Input voltage sensing for on-time control and telemetry and negative terminal of the input current sensing shunt; short to CSPIN if input current sensing is not used. |
| 39 | V3P3 | power_in | 3.3-V power input that powers all digital logic; bypass to GND with a ceramic capacitor of at least 1 µF. |
| 40 | VREF | power_in | 1.7-V LDO reference voltage; bypass to GND with 1 µF ceramic and connect to REFIN of TI smart power stages as the current sense common-mode voltage. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-40-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 41 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage CSPIN, VIN_CSNIN | -0.3 | 19 | V | 6 | |||
| Input voltage ACSP1-ACSP6/BCSP3, ADDR, ATSEN, AVR_EN, AVSP, BCSP1, BCSP2, BTSEN, BVR_EN, BVSP, RESET, SMB_CLK, SMB_DIO, V3P3 | -0.3 | 3.6 | V | 6 | |||
| Input voltage AGND, AVSN, BVSN | -0.3 | 0.3 | V | 6 | |||
| Output voltage APWM1-APWM6/BPWM3, BPWM1, BPWM2, AVR_RDY, BVR_RDY, SMB_ALERT, VREF, VR_FAULT, VR_HOT | -0.3 | 3.6 | V | 6 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 6 | ||
| Storage temperature | TSTG | -55 | 150 | °C | 6 | ||
| Input voltage CSPIN, VIN_CSNIN | 4.5 | 12 | 17 | V | 6 | ||
| V3P3 supply voltage | V3P3 | 2.97 | 3.3 | 3.5 | V | 6 | |
| Input voltage ACSP1-ACSP6/BSCP3, ADDR, ATSEN, AVR_EN, AVSP, BCSP1, BCSP2, BTSEN, BVR_EN, BVSP, RESET, SMB_CLK, SMB_DIO, V3P3 | -0.1 | 3.5 | V | 6 | |||
| Input voltage AGND, AVSN, BVSN | -0.1 | 0.1 | V | 6 | |||
| Output voltage VREF | VREF | -0.1 | 1.72 | V | 6 | ||
| Output voltage APWM1-APWM6/BPWM3, BPWM2, AVR_RDY, BPWM1, BVR_RDY, SMB_ALERT, VREF, VR_FAULT, VR_HOT | -0.1 | 3.5 | V | 6 | |||
| Ambient temperature | TA | -40 | 125 | °C | 6 | ||
| V3P3 supply current | IV3P3 | 13 | 18 | mA | VDAC < VSP < VDAC + 100mV, ENABLE = HI | 7 | |
| V3P3 standby current | IV3P3SBY | 9 | 13.5 | mA | ENABLE = LO | 7 | |
| V3P3 normal range | V3NORMAL | 2.97 | 3.5 | V | Normal operation | 7 | |
| VREF output deeper sleep | VVREF | 1.692 | 1.7 | 1.708 | V | 2.97V ≤ VV3P3 ≤ 3.5 V, IVREF = 0 A | 8 |
| Fixed overvoltage protection, Channel A | VOVPA | 2.75 | 2.8 | 2.86 | V | VAVSP > VOVP for 1 µs, ENABLE = HI or LO, PWM to LO | 22 |
| Fixed overvoltage protection, Channel B | VOVPB | 1.85 | 1.9 | 1.95 | V | VBVSP > VOVP for 1 µs, ENABLE = HI or LO, PWM to LO | 22 |
| VREAD_VOUT accuracy | VREAD_VOUT | -12 | 12 | mV | 5 mV DAC: 0.25 V ≤ VVSP ≤ 1.52 V; 10 mV DAC: 0.5 ≤ VVSP ≤ 2.4 V | 9 | |
| READ_VIN accuracy | VREAD_VIN | -2.25 | 2.25 | % | 4.50 V ≤ VIN ≤ 17 V | 9 | |
| Temp READ_TEMP1 accuracy | Temp | -2 | 0 | 2 | °C | 0.28 V (-40°C) ≤ TSEN ≤ 1.8 V (150°C) | 9 |
| IIN READ_IIN accuracy | IIN | -10 | 10 | % | (VCSPIN, VCSNIN) = 2.5 mV, IIN = 5 A, RSENSE = 0.5 mΩ | 10 | |
| TSEN leakage current | ITSEN | -3 | 3 | µA | 22 | ||
| Switching frequency | fSW | 360 | 400 | 440 | kHz | FREQUENCY_SWITCH = 0x0190, VIN = 12 V, VAVSP = 1.0 V, VBVSP = 0.8 V, TA = 25°C | 19 |
| Channel A startup time | tSTARTUPA | 0.38 | 0.48 | 0.58 | ms | VVBOOT > 0 V, no faults, CREF = 1 µF, TON_DELAY = 0xB1EC (PAGE 0) | 16 |
| Junction-to-ambient thermal resistance | RθJA | 34.1 | °C/W | 7 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 16.6 | °C/W | 7 | |||
| Junction-to-board thermal resistance | RθJB | 5.8 | °C/W | 7 | |||
| Junction-to-top characterization parameter | ψJT | 0.2 | °C/W | 7 | |||
| Junction-to-board characterization parameter | ψJB | 5.7 | °C/W | 7 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 0.9 | °C/W | 7 |
CAD (KiCad official)
- Symbol:
TPS53681RSBT - Footprint:
Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm - 3D model: QFN-40-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps53681rsbt-etched.step/tps53681rsbt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps53681rsbt.step/tps53681rsbt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (131 pp, sha256
91eb09650cc2e250, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).