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TPS51125ARGET

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps51125argetfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TPS51125ARGET

Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)

TPS51125ARGET from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ENTRIP1 bidirectional Channel 1 enable/disable and overcurrent limit setting input; connect resistor to GND for RDS(on) sense threshold or short to GND to shut down channel.
2 VFB1 input Channel 1 feedback input for output voltage regulation via resistor divider.
3 VREF power_out 2-V reference voltage output; bypass with 220 nF to 1 μF capacitor to GND.
4 TONSEL input On-time frequency selection input; voltage level selects operating frequency between 200 kHz and 460 kHz.
5 VFB2 input Channel 2 feedback input for output voltage regulation via resistor divider.
6 ENTRIP2 bidirectional Channel 2 enable/disable and overcurrent limit setting input; connect resistor to GND for RDS(on) sense threshold or short to GND to shut down channel.
7 VO2 bidirectional Channel 2 SMPS output node; serves as voltage reference, discharge path, and 3.3-V return power input.
8 VREG3 power_out 3.3-V power supply output; bypass with 10 μF or larger ceramic capacitor to GND (minimum 1 μF acceptable at no load).
9 VBST2 power_in Boost voltage supply input for channel 2 high-side gate driver.
10 DRVH2 output Channel 2 high-side N-channel MOSFET driver output, referenced to LL2.
11 LL2 input Channel 2 switch node connection for high-side driver and current sense circuitry.
12 DRVL2 output Channel 2 low-side N-channel MOSFET driver output, GND-referenced.
13 EN0 bidirectional Master enable input; open for LDO enable with switcher ready, 620 kΩ to GND for LDO enable without switcher, or short to GND to disable all circuits.
14 SKIPSEL input Operating mode selection input; voltage level selects between PWM-only, auto skip, and out-of-audio modes.
15 GND power_in Ground reference.
16 VIN power_in Main power supply input for LDO and controller; operating range 5.5 V to 28 V.
17 VREG5 power_out 5-V power supply output; bypass with 10 μF or larger ceramic capacitor to GND.
18 VCLK output 270-kHz clock output for external charge pump gate driver.
19 DRVL1 output Channel 1 low-side N-channel MOSFET driver output, GND-referenced.
20 LL1 input Channel 1 switch node connection for high-side driver and current sense circuitry.
21 DRVH1 output Channel 1 high-side N-channel MOSFET driver output, referenced to LL1.
22 VBST1 power_in Boost voltage supply input for channel 1 high-side gate driver.
23 PGOOD output Power-good logic AND output indicating both channels within regulation window.
24 VO1 bidirectional Channel 1 SMPS output node; serves as voltage reference, discharge path, and 5-V return power input.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

CAD (KiCad official)

  • Symbol: TPS51125ARGET
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps51125arget-etched.step / tps51125arget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps51125arget.step / tps51125arget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 5778180f95295476, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF