component
MC100EP52DG
Public Made by Adomby adom
onsemi Flip Flops, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMC100EP52DG
onsemi · Flip Flops · SOIC-8
MC100EP52DG from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | input | True ECL data input, which defaults LOW when left open and has an internal 75 kΩ pulldown to VEE. |
| 2 | D̄ | input | Complementary ECL data input, which defaults LOW when left open and has an internal 75 kΩ pulldown to VEE. |
| 3 | CLK | input | True ECL clock input, which defaults LOW when left open; data is transferred to the outputs on its LOW-to-HIGH transition. |
| 4 | CLK̄ | input | Complementary ECL clock input, which defaults LOW when left open and has an internal 75 kΩ pulldown to VEE. |
| 5 | VEE | power_in | Negative supply, 0 V in PECL mode or −3.0 V to −5.5 V in NECL mode. |
| 6 | Q̄ | output | Complementary ECL data output, terminated with 50 Ω to VCC − 2.0 V. |
| 7 | Q | output | True ECL data output, which defaults LOW with inputs open or at VEE and is terminated with 50 Ω to VCC − 2.0 V. |
| 8 | VCC | power_in | Positive supply, 3.0 V to 5.5 V in PECL mode or 0 V in NECL mode. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Logic ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| PECL Mode Power Supply | VCC | 6 | V | VEE = 0 V | 3 | ||
| NECL Mode Power Supply | VEE | -6 | V | VCC = 0 V | 3 | ||
| PECL Mode Input Voltage | VI | 6 | V | VEE = 0 V, VI ≤ VCC | 3 | ||
| NECL Mode Input Voltage | VI | -6 | V | VCC = 0 V, VI ≥ VEE | 3 | ||
| Output Current Continuous | Iout | 50 | mA | Continuous | 3 | ||
| Output Current Surge | Iout | 100 | mA | Surge | 3 | ||
| VBB Sink/Source Current | IBB | -0.5 | 0.5 | mA | 3 | ||
| Operating Temperature Range | TA | -40 | 85 | °C | 3 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 3 | ||
| Thermal Resistance Junction-to-Ambient, SOIC-8 NB | θJA | 190 | °C/W | 0 lfpm, SOIC-8 NB | 3 | ||
| Thermal Resistance Junction-to-Ambient, SOIC-8 NB | θJA | 130 | °C/W | 500 lfpm, SOIC-8 NB | 3 | ||
| Thermal Resistance Junction-to-Case, SOIC-8 NB | θJC | 41 | 44 | °C/W | Standard Board, SOIC-8 NB | 3 | |
| Wave Solder (Pb-Free) | Tsol | 265 | °C | < 2 to 3 sec @ 260°C | 3 | ||
| Power Supply Current | IEE | 20 | 34 | 44 | mA | 100EP DC, -40°C | 5 |
| Power Supply Current | IEE | 20 | 35 | 45 | mA | 100EP DC, 25°C | 5 |
| Power Supply Current | IEE | 20 | 37 | 47 | mA | 100EP DC, 85°C | 5 |
| Output HIGH Voltage | VOH | 2155 | 2280 | 2405 | mV | PECL VCC = 3.3 V, VEE = 0 V; -40/25/85°C; 50 Ω to VCC − 2.0 V | 5 |
| Output LOW Voltage | VOL | 1355 | 1480 | 1605 | mV | PECL VCC = 3.3 V, VEE = 0 V; -40/25/85°C; 50 Ω to VCC − 2.0 V | 5 |
| Input HIGH Voltage (Single-Ended) | VIH | 2075 | 2420 | mV | PECL VCC = 3.3 V, VEE = 0 V; -40/25/85°C | 5 | |
| Input LOW Voltage (Single-Ended) | VIL | 1355 | 1675 | mV | PECL VCC = 3.3 V, VEE = 0 V; -40/25/85°C | 5 | |
| Input HIGH Voltage Common Mode Range | VIHCMR | 2 | 3.3 | V | PECL VCC = 3.3 V, differential configuration; -40/25/85°C | 5 | |
| Output HIGH Voltage | VOH | 3855 | 3980 | 4105 | mV | PECL VCC = 5.0 V, VEE = 0 V; -40/25/85°C; 50 Ω to VCC − 2.0 V | 5 |
| Output LOW Voltage | VOL | 3055 | 3180 | 3305 | mV | PECL VCC = 5.0 V, VEE = 0 V; -40/25/85°C; 50 Ω to VCC − 2.0 V | 5 |
| Input HIGH Voltage (Single-Ended) | VIH | 3775 | 4120 | mV | PECL VCC = 5.0 V, VEE = 0 V; -40/25/85°C | 5 | |
| Input LOW Voltage (Single-Ended) | VIL | 3055 | 3375 | mV | PECL VCC = 5.0 V, VEE = 0 V; -40/25/85°C | 5 | |
| Input HIGH Voltage Common Mode Range | VIHCMR | 2 | 5 | V | PECL VCC = 5.0 V, differential configuration; -40/25/85°C | 5 | |
| Output HIGH Voltage | VOH | -1145 | -1020 | -895 | mV | NECL VCC = 0 V, VEE = −5.5 V to −3.0 V; -40/25/85°C; 50 Ω to VCC − 2.0 V | 6 |
| Output LOW Voltage | VOL | -1945 | -1820 | -1695 | mV | NECL VCC = 0 V, VEE = −5.5 V to −3.0 V; -40/25/85°C; 50 Ω to VCC − 2.0 V | 6 |
| Input HIGH Voltage (Single-Ended) | VIH | -1225 | -880 | mV | NECL VCC = 0 V, VEE = −5.5 V to −3.0 V; -40/25/85°C | 6 | |
| Input LOW Voltage (Single-Ended) | VIL | -1945 | -1625 | mV | NECL VCC = 0 V, VEE = −5.5 V to −3.0 V; -40/25/85°C | 6 | |
| Input HIGH Voltage Common Mode Range (min, referenced to VEE) | VIHCMR | 2 | 0 | V | NECL, differential configuration; min printed as VEE+2.0 (value shown is the +2.0 offset), max 0.0; -40/25/85°C | 6 | |
| Input HIGH Current | IIH | 150 | µA | -40/25/85°C | 5 | ||
| Input LOW Current | IIL | 0.5 | µA | -40/25/85°C | 5 | ||
| Output Voltage Amplitude @ 3.0 GHz | VOUTpp | 630 | 750 | mV | -40°C; Figure 2 | 6 | |
| Output Voltage Amplitude @ 3.0 GHz | VOUTpp | 610 | 730 | mV | 25°C; Figure 2 | 6 | |
| Output Voltage Amplitude @ 3.0 GHz | VOUTpp | 520 | 640 | mV | 85°C; Figure 2 | 6 | |
| Propagation Delay CLK, CLK to Q, Q | tPLH, tPHL | 250 | 300 | 350 | ps | -40°C | 6 |
| Propagation Delay CLK, CLK to Q, Q | tPLH, tPHL | 280 | 330 | 380 | ps | 25°C | 6 |
| Propagation Delay CLK, CLK to Q, Q | tPLH, tPHL | 310 | 360 | 410 | ps | 85°C | 6 |
| Setup Time | tS | 50 | ps | -40/25/85°C | 6 | ||
| Hold Time | tH | 0 | ps | -40/25/85°C | 6 | ||
| CLOCK Random Jitter (RMS) | tJITTER | 0.2 | 1 | ps | -40/25/85°C; Figure 2 | 6 | |
| Input Voltage Swing (Differential Configuration) | VPP | 150 | 800 | 1200 | mV | -40/25/85°C | 6 |
| Output Rise/Fall Times (20%-80%) Q, Q | tr, tf | 70 | 110 | 170 | ps | -40°C | 6 |
| Output Rise/Fall Times (20%-80%) Q, Q | tr, tf | 80 | 120 | 180 | ps | 25°C | 6 |
| Output Rise/Fall Times (20%-80%) Q, Q | tr, tf | 90 | 130 | 200 | ps | 85°C | 6 |
CAD (KiCad official)
- Symbol:
MC100EP52DG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mc100ep52dg-etched.step/mc100ep52dg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc100ep52dg.step/mc100ep52dg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
3717bbe03065e828, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).