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CA-IS3722HG

Public Made by Adom

by adom

Chipanalog Digital Isolators, SOIC-8-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsignal isolation devicesca-is3722hgfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CA-IS3722HG

Chipanalog · Digital Isolators · SOIC-8-300mil

CA-IS3722HG from Chipanalog, in a SOIC-8-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side-A supply voltage, recommended range 2.375 V to 5.5 V, with absolute maximum rating of -0.5 V to 7.0 V.
2 VO1 output Side-A logic output of channel 1 on the CA-IS3722; rail-to-rail with 50 Ω typical output impedance, IOH = -4 mA and IOL = 4 mA at 5 V.
3 VI2 input Side-A logic input of channel 2 on the CA-IS3722; Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V, and input voltage limited to -0.5 V to VDD + 0.5 V.
4 GNDA power_in Side-A ground reference; all Side-A voltages are measured relative to GNDA.
5 GNDB power_in Side-B ground reference; all Side-B voltages are measured relative to GNDB.
6 VO2 output Side-B logic output of channel 2 on the CA-IS3722; rail-to-rail with 50 Ω typical output impedance, IOH = -4 mA and IOL = 4 mA at 5 V.
7 VI1 input Side-B logic input of channel 1 on the CA-IS3722; Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V, and input voltage limited to -0.5 V to VDD + 0.5 V.
8 VDDB power_in Side-B supply voltage, recommended range 2.375 V to 5.5 V, with absolute maximum rating of -0.5 V to 7.0 V.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-8-300mil
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB -0.5 7 V 6
Input voltage Ax, Bx, ENx (printed max VDD+0.5, footnote 3) Vin -0.5 V 6
Output current IO IO -20 20 mA 6
Junction temperature TJ 150 °C 6
Storage temperature range TSTG -65 150 °C 6
Supply voltage VDDA, VDDB VDDA, VDDB 2.375 3.3 5.5 V 6
VDD undervoltage threshold, rising (UVLO+) VDD(UVLO+) 1.95 2.24 2.375 V 6
VDD undervoltage threshold, falling (UVLO-) VDD(UVLO-) 1.88 2.1 2.325 V 6
VDD undervoltage hysteresis VHYS(UVLO) 70 140 250 mV 6
High-level output current IOH IOH -4 mA VDDO = 5 V 6
Low-level output current IOL IOL 4 mA VDDO = 5 V 6
Input threshold logic high VIH 2 V 6
Input threshold logic low VIL 0.8 V 6
Signaling data rate DR 0 150 Mbps 6
Ambient temperature TA -40 27 125 °C 6
Maximum power dissipation, total PD 120 mW CA-IS3722; VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75 MHz 50% duty input 7
Maximum power dissipation, A side PDA 60 mW CA-IS3722; VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75 MHz 50% duty input 7
Maximum power dissipation, B side PDB 60 mW CA-IS3722; VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75 MHz 50% duty input 7
External clearance (G/W package) CLR 8 mm Input to output, shortest distance through air 8
External creepage (G/W package) CPG 8 mm Input to output, shortest distance along package body 8
Internal isolation distance DTI DTI 19 µm Minimum internal gap 8
Comparative tracking index CTI CTI 600 V DIN EN 60112 (VDE 0303-11); IEC 60112; printed >600 8
Maximum working isolation voltage VIOWM (AC) VIOWM 600 VRMS AC voltage; time-dependent dielectric breakdown (TDDB) test (G/W package) 8
Maximum transient isolation voltage VIOTM VIOTM 7070 VPK VTEST = VIOTM, t = 60 s (certification) 8
Isolation voltage VISO VISO 5000 VRMS UL 1577; VTEST = VISO, t = 60 s (certification) 8
Low-level output voltage VOL VOL 0.2 0.4 V IOL = 4 mA; Fig 8-1 10
Positive input threshold VIT+(IN) VIT+(IN) 1.4 1.67 1.9 V 10
Negative input threshold VIT-(IN) VIT-(IN) 1 1.23 1.4 V 10
Input threshold hysteresis VI(HYS) VI(HYS) 0.3 0.44 0.5 V 10
Input high-level leakage current IIH IIH 20 µA VIH = VDDA at Ax or Bx or ENx 10
Input low-level leakage current IIL IIL -20 µA VIL = 0 V at Ax or Bx 10
Common-mode transient immunity CMTI CMTI 100 150 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; Fig 8-3 10
Output impedance tolerance (normal isolator channel, note 2) ZO -40 40 % Normal isolator channel; printed ±40% 10
Input high-level current VOH (printed min VDDO1-0.4) VOH 4.8 V IOH = -4 mA; Fig 8-1 10
Output impedance ZO ZO 50 Ω Normal isolator channel 10
Quiescent supply current IDDA, DC signal (CA-IS3722H) IDDA 1.5 3 mA VIN = VDDI (CA-IS3722H), DC signal 11
Quiescent supply current IDDB, DC signal (CA-IS3722H) IDDB 1.5 3 mA VIN = VDDI (CA-IS3722H), DC signal 11
Supply current IDDA, AC signal IDDA 1.6 2.9 mA 1 Mbps (500 kHz); 50% duty square wave; CL = 15 pF per channel 11
Supply current IDDB, AC signal IDDB 1.7 3 mA 1 Mbps (500 kHz); 50% duty square wave; CL = 15 pF per channel 11
Supply current IDDB, AC signal IDDB 2.7 4 mA 10 Mbps (5 MHz); 50% duty square wave; CL = 15 pF per channel 11
Supply current IDDB, AC signal IDDB 12.7 18.2 mA 100 Mbps (50 MHz); 50% duty square wave; CL = 15 pF per channel 11
Data rate DR DR 0 150 Mbps 14
Minimum pulse width PWmin PWmin 5 ns 14
Propagation delay tPLH, tPHL tPLH, tPHL 5 12 15 ns Fig 8-1 14
Pulse width distortion PWD PWD 0.2 4.5 ns /tPLH - tPHL/ 14
Channel-to-channel output skew tsk(o) tsk(o) 0.4 2.5 ns Same-direction channels, single device (note 1) 14
Part-to-part channel output skew tsk(pp) tsk(pp) 2 4.5 ns Same supply voltage, temperature, input and load (note 2) 14
Output rise time tr tr 2.5 4 ns Fig 8-1 14
Output fall time tf tf 2.5 4 ns Fig 8-1 14
Default output delay time from input power loss tDO tDO 8 12 ns Fig 8-2 14
Startup time tSU tSU 15 40 µs 14
Junction-to-ambient thermal resistance RθJA RθJA 92.3 °C/W SOIC8-WB(G) package 7

CAD (KiCad official)

  • Symbol: CA-IS3722HG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3722hg-etched.step / ca-is3722hg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3722hg.step / ca-is3722hg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (25 pp, sha256 fe7c518865098110, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF