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LTC4218IGN#TRPBF

Analog Devices · Surge Protection Devices (SPDs) · SSOP-16-150mil

LTC4218IGN#TRPBF from Analog Devices, in a SSOP-16-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENSE+ input Current sense plus input, connected to the VDD side of the current sense resistor; the current limit holds the SENSE+ to SENSE- voltage to 15mV or less depending on the FB voltage.
2 SENSE- input Current sense minus input, connected to the side of the current sense resistor opposite VDD; the current limit holds the SENSE+ to SENSE- voltage to 15mV or less depending on the FB voltage.
3 ISET passive Current limit adjustment pin; leave open for the 15mV threshold, keep any RSET resistor no less than 2kΩ due to circuit tolerance, and place a 0.1µF capacitor to ground when a board trace connects to this pin.
4 IMON output Current monitor output that sources 6.67µA/mV of sense voltage, giving a 0V to 2V swing with a 20kΩ resistor to GND for a 0mV to 15mV sense voltage, with compliance from 0V to INTVCC - 0.7V.
5 FB input Foldback and power good comparator input; below 0.6V the current limit is reduced, and below 1.21V the PG pin pulls low on the adjustable LTC4218.
6 FLT output Open-drain overcurrent fault indicator that pulls low when the circuit breaker trips, and is tied to UV for overcurrent auto-retry.
7 PG output Open-drain power good indicator that pulls low when FB falls below 1.21V and releases high once FB rises above 1.23V and GATE-to-SOURCE exceeds 4.2V.
8 GATE output Gate drive for the external N-channel MOSFET, charged by a 24µA current source, pulled down by 250µA during UV/OV turn-off and by 170mA during a short circuit or undervoltage lockout.
9 SOURCE passive N-channel MOSFET source connection, which connects to the source of the external MOSFET and provides the return for the gate pull-down circuit.
10 GND power_in Device ground.
11 INTVCC power_out Internal 3.1V supply decoupling output that requires a 1µF or larger capacitor, and overloading this pin can disrupt internal operation.
12 TIMER passive Timer input; a capacitor to ground sets a 12ms/µF current-limit duration before the switch turns off, with a 1.2V high threshold and 0.2V low threshold.
13 OV input Overvoltage comparator input; if the voltage rises above 1.235V the switch turns off, and the pin must be tied to GND if unused.
14 UV input Undervoltage comparator input; the switch turns off when the voltage falls below 1.15V, pulling it below 0.62V resets an overcurrent fault, and it must be tied high if unused.
15 VDD power_in Supply voltage input with an operating range of 2.9V to 26.5V and an undervoltage lockout threshold of 2.73V.
16 NC unconnected No connection.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SSOP-16-150mil
Category Circuit Protection
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Supply Range VDD 2.9 26.5 V 3
Input Supply Undervoltage Lockout VDD(UVL) 2.65 2.73 2.85 V VDD Rising 3
Current Limit Sense Voltage Threshold (VSENSE+, VSENSE-) ΔVSNS(TH) 14.25 15 15.75 mV VFB = 1.23V 3
Current Limit Sense Voltage Threshold (VSENSE+, VSENSE-) ΔVSNS(TH) 2.8 3.75 4.7 mV VFB = 0V 3
Current Limit Sense Voltage Threshold (VSENSE+, VSENSE-) ΔVSNS(TH) 6.7 7.5 8.325 mV VFB = 1.23V, RSET = 20kΩ 3
SENSE- Input Current ISENSE-(IN) -10 4 10 µA VSENSE- = 12V 3
SENSE+ Input Current ISENSE+(IN) -20 5.5 20 µA VSENSE+ = 12V 3
External N-Channel Gate Drive (VGATE, VSOURCE) ΔVGATE 5 6.15 6.5 V VDD = 2.9V to 26.5V (Note 3), IGATE = 0, -1µA 3
Gate High Threshold (VGATE, VSOURCE) ΔVGATE-HIGH(TH) 3.5 4.2 4.8 V 3
External N-Channel Gate Pull-Up Current IGATE(UP) -29 -24 -19 µA Gate Drive On, VGATE = VSOURCE = 12V 3
External N-Channel Gate Fast Pull-Down Current IGATE(FST) 100 170 220 mA Fast Turn Off, VGATE = 18V, VSOURCE = 12V 3
External N-Channel Gate Pull-Down Current IGATE(DN) 200 250 400 µA Gate Drive Off, VGATE = 18V, VSOURCE = 12V 3
OV, UV, FB Input Current IIN -1 0 1 µA VPIN = 1.2V, LTC4218 Only 3
OV, UV, FB Threshold Voltage V(TH) 1.21 1.235 1.26 V VPIN Rising 3
OV Hysteresis ΔVOV(HYST) 10 20 30 mV 3
UV Hysteresis ΔVUV(HYST) 50 80 110 mV 3
UV Reset Threshold Voltage VUV(RTH) 0.55 0.62 0.7 V VUV Falling 3
FB Power Good Hysteresis ΔVFB(HYST) 10 20 30 mV 3
ISET Internal Resistor RISET 19.5 20 20.5 kΩ 3
SOURCE Input Current ISOURCE 1 2 4 µA VSOURCE = VGATE = 12V, LTC4218 Only 3
SOURCE Input Current ISOURCE -1 0 1 µA VSOURCE = VGATE = 0V 3
TIMER High Threshold VTIMER(H) 1.2 1.235 1.28 V VTIMER Rising 3
TIMER Low Threshold VTIMER(L) 0.1 0.21 0.3 V VTIMER Falling 3
TIMER Pull Up Current ITIMER(UP) -120 -100 -80 µA VTIMER = 0V 3
TIMER Pull-Down Current ITIMER(DN) 1.4 2 2.6 µA VTIMER = 1.2V 3
TIMER Current Ratio ITIMER(RATIO) 1.6 2 2.7 % ITIMER(DN)/ITIMER(UP) 4
IMON Full-Scale Output Current IMON(FS) 94 100 106 µA VSENSE+, VSENSE- = 15mV 4
IMON Offset Current IMON(OFF) -6 0 6 µA VSENSE+, VSENSE- = 1mV 4
IMON Gain GIMON 6.47 6.67 6.87 µA/mV VSENSE+, VSENSE- = 15mV and 1mV 4
PG, FLT Output Low Voltage VOL 0.4 0.8 V ISINK = 2mA 3
PG, FLT Input Leakage Current IOH -10 0 10 µA V = 30V 3
Input Supply Current IDD 1.6 5 mA FET On 3
Input High (OV), Input Low (UV) to GATE Low Propagation Delay tPHL(GATE) 3 5 µs VGATE < 16.5V Falling 4
VSENSE+, VSENSE- High to GATE Low Propagation Delay tPHL(SENSE) 0.2 1 µs VFB = 0, Step (VSENSE+, VSENSE-) to 60mV, CGATE = 1.5nF, VGATE < 16.5V Falling 4
Turn-On Delay tD(ON) 50 100 150 ms Step VUV to 2V, VGATE > 13V 4
Supply Voltage VDD -0.3 35 V 2
Input Voltages FB, OV, UV VFB, VOV, VUV -0.3 12 V 2
Input Voltage TIMER VTIMER -0.3 3.5 V 2
Input Voltage SOURCE VSOURCE -5 V Upper limit printed as VDD + 0.3V 2
Output Voltages ISET, IMON VISET, VIMON -0.3 3 V 2
Output Voltages PG, FLT VPG, VFLT -0.3 35 V 2
Output Voltage INTVCC VINTVCC -0.3 3.5 V 2
Output Voltage GATE VGATE -0.3 35 V Note 3 2
Operating Ambient Temperature Range (LTC4218I) TA -40 85 °C 2
Storage Temperature Range TSTG -65 150 °C 2
Maximum Junction Temperature TJMAX 150 °C GN package 2
VINTVCC INTVCC Output Voltage VINTVCC 3.1 V ISINK = 0mA, -10mA 3
Bandwidth IMON BWIMON 250 kHz 4
Fault Latch Clear Delay (UV Low to Clear Fault Latch) tD(FAULT) 1 µs 4
Thermal Resistance Junction-to-Ambient θJA 135 °C/W GN package 2

CAD (KiCad official)

  • Symbol: LTC4218IGN#TRPBF
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16-150mil (KiCad packages3D, STEP)
  • 3D model files: ltc4218ign-trpbf-etched.step / ltc4218ign-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc4218ign-trpbf.step / ltc4218ign-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (18 pp, sha256 427d5758f9234b2a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF