component
FU6831N
Public Made by Adomby adom
Fortior Tech Microcontrollers (MCU/MPU/SOC), QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownFU6831N
Fortior Tech · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(4x4)
FU6831N from Fortior Tech, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P2.6/C3M | bidirectional | GPIO with configurable external interrupt INT1 input; serves as the overcurrent reference signal input and the negative input of comparator CMP3. |
| 2 | P2.7/AD4/C3P/A0O | bidirectional | GPIO with configurable INT1 input; ADC channel 4 input for the amplified bus-current signal, positive input of CMP3 for bus-current overcurrent detection, and AMP0 output carrying the amplified bus-current voltage. |
| 3 | P3.0/A0M | bidirectional | GPIO; negative input of AMP0, used to amplify the bus-current signal. |
| 4 | P3.1/A0P | bidirectional | GPIO; positive input of AMP0, used to amplify the bus-current signal. |
| 5 | P3.2/AD5/TIM0/VHALF | bidirectional | GPIO; over-temperature signal input and ADC channel 5 input, also Advanced timer channel 4 output and 1/2 VDD5 or 1/2 VREF reference output that requires an external 1 µF capacitor. |
| 6 | P3.4/AD7/TXD2/IR_TXD2 | bidirectional | GPIO; analog speed-control input on ADC channel 7, with UART2 transmit and infrared transmit functions after function transfer. |
| 7 | P3.5/VREF | bidirectional | GPIO; ADC external reference voltage input or internal VREF output, requiring an external 1 µF capacitor. |
| 8 | AVSS | power_in | Analog ground. |
| 9 | AVDD5 | power_in | Analog supply input, connected externally to VDD5 with a 1 µF capacitor to AVSS. |
| 10 | P0.0/SDA | bidirectional | GPIO with configurable INT0 input; I2C SDA open-drain output with optional 4.7 kΩ pull-up. |
| 11 | P0.1/SCL/TIM4 | bidirectional | GPIO; I2C SCL clock open-drain output with optional 4.7 kΩ pull-up, or Timer4 input/output. |
| 12 | P1.4/C0P/P2.4/AD2 | bidirectional | Multiplexed pin: P1.4 GPIO with INT1 and optional 4.7 kΩ pull-up, Timer1 switch Hall0 input and differential Hall0/BEMF0 positive input; or P2.4 GPIO with INT1 and ADC channel 2 input for the bus-voltage signal. |
| 13 | P0.5/MOSI/TXD/IR_TXD | bidirectional | GPIO; SPI MOSI (master output or slave input), UART1 transmit and infrared transmit before function transfer. |
| 14 | P0.6/MISO/RXD/IR_RXD | bidirectional | GPIO; SPI MISO (master input or slave output), UART1 receive and infrared receive before function transfer. |
| 15 | P0.7/SCLK/TIM5/CXO | bidirectional | GPIO; SPI clock, Timer5 capture input or PWM output, and comparator output test pin. |
| 16 | P1.1/TIM3 | bidirectional | GPIO with configurable INT1 input; Timer3 capture input or PWM output. |
| 17 | H_PU | output | 3P3N Predriver high-side U-phase voltage output with internal 47 kΩ pull-up. |
| 18 | H_PV | output | 3P3N Predriver high-side V-phase voltage output with internal 47 kΩ pull-up. |
| 19 | H_PW | output | 3P3N Predriver high-side W-phase voltage output with internal 47 kΩ pull-up. |
| 20 | L_U | output | 3P3N Predriver low-side U-phase voltage output with internal 47 kΩ pull-down. |
| 21 | L_V | output | 3P3N Predriver low-side V-phase voltage output with internal 47 kΩ pull-down. |
| 22 | L_W | output | 3P3N Predriver low-side W-phase voltage output with internal 47 kΩ pull-down. |
| 23 | VBB | power_out | 10 V LDO output; connect an external 1 µF to 4.7 µF capacitor. |
| 24 | VCC | power_in | Power input for an external 5 V to 24 V supply, with VDD5 generated by the internal LDO; add a 10 µF or larger filter capacitor. |
| 25 | VSS | power_in | Digital ground. |
| 26 | VDD5 | power_out | Internal 5 V LDO output supply; connect an external 1 µF to 4.7 µF capacitor. |
| 27 | RSTN/FICEK | input | External reset input with internal pull-up; also the FICE debug interface clock. |
| 28 | VDD18 | power_out | 1.85 V LDO output; connect an external 1 µF to 4.7 µF capacitor. |
| 29 | P1.2/FICED | bidirectional | GPIO with configurable INT1 input; FICE debug interface data port. |
| 30 | P1.3/HBIAS | bidirectional | GPIO; Hall bias supply switched internally to VDD5, capable of high-current output. |
| 31 | P1.6/C1P/P2.0/AD0 | bidirectional | Multiplexed pin: P1.6 GPIO with INT1 and optional 4.7 kΩ pull-up, Timer1 switch Hall1 input and differential Hall1/BEMF1 positive input; or P2.0 GPIO with INT1 and ADC channel 0 input for the amplified phase-current 1 signal. |
| 32 | P2.1/C2P/P2.3/AD1 | bidirectional | Multiplexed pin: P2.1 GPIO with INT1 and optional 4.7 kΩ pull-up, Timer1 switch Hall2 input and differential Hall2/BEMF2 positive input; or P2.3 GPIO with INT1 and ADC channel 1 input for the amplified phase-current 2 signal. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Fortior Tech |
| Package | QFN-32-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| TJ工作时结温 (junction temperature, operating) | TJ | -40 | 150 | ℃ | 68 | ||
| 储存温度 (storage temperature) | -55 | 150 | ℃ | 68 | |||
| VCC 相对 VSS 的电压 (VCC to VSS voltage) | VCC | -0.3 | 36 | V | 68 | ||
| VDD5 相对 VSS 的电压 (VDD5 to VSS voltage) | VDD5 | -0.3 | 6.5 | V | 68 | ||
| RSTN、VCC_MODE、GPIO 相对 VSS 的电压 (RSTN, VCC_MODE, GPIO to VSS voltage) | -0.3 | V | 68 | ||||
| VCC 工作电压, 单电源高压模式 (single-supply high-voltage mode) | VCC | 5 | 24 | V | 单电源高压模式, TA = -40℃ ~ 85℃ | 71 | |
| VCC 工作电压, 双电源高压模式 (dual-supply high-voltage mode) | VCC | 5 | 36 | V | 双电源高压模式, VCC_MODE = 1, VCC ≥ VDD5 | 71 | |
| IVCC睡眠电流 (sleep current) | IVCC | 100 | 250 | μA | TA = 25℃, VCC = 15V, VCC_MODE = 0 | 71 | |
| 工作时环境温度 TA (operating ambient temperature) | TA | -40 | 85 | ℃ | 71 | ||
| 工作时环境温度 TA (operating ambient temperature, VCC_MODE = VDD5 = 5V) | TA | -40 | 105 | ℃ | VCC_MODE = VDD5 = 5V, VCC ≤ 24V | 71 | |
| 采样时间 (sampling time, 12-bit mode) | 3 | 63 | ADCLK | 79 | |||
| VREF 参考电压, VREF_CR[VREFVSEL] = 10 (reference voltage) | VREF | 4.3 | 4.5 | 4.7 | V | VREF_CR[VREFVSEL] = 10, TA = -40℃ ~ 85℃, VCC = 15V, VCC_MODE = 0 | 80 |
| VICMR 运放共模输入范围下限 (op-amp common-mode input range, min) | VICMR | 0 | V | TA = 25℃, VCC = 15V, VCC_MODE = 0 | 80 | ||
| VOS 运放失配电压 (op-amp offset voltage) | VOS | 5 | 10 | mV | TA = 25℃ | 80 | |
| UGBW 单位增益带宽 (unity-gain bandwidth) | UGBW | 6 | 10 | MHz | CL = 40pF | 80 | |
| SR 运放摆率 (slew rate) | SR | 10 | 15 | V/μs | CL = 40pF | 80 | |
| VICMR 比较器共模输入范围下限 (comparator common-mode input range, min) | VICMR | 0 | V | TA = 25℃, VCC = 15V, VCC_MODE = 0 | 80 | ||
| BEMF 内置电阻 (built-in BEMF resistance) | 5.4 | 6.8 | 8.2 | KΩ | TA = 25℃, VCC = 15V, VCC_MODE = 0 | 81 | |
| 系统时钟频率 (system clock frequency) | 23.5 | 24 | 24.5 | MHz | TA = -40℃ ~ 85℃, VCC = 5V ~ 24V, VCC_MODE = 0 | 81 | |
| 低速时钟频率 (low-speed clock frequency) | 29 | 32.8 | 37 | KHz | TA = -40℃ ~ 85℃, VCC = 5V ~ 24V, VCC_MODE = 0 | 81 | |
| RSTN 复位低电平最小宽度 (reset low pulse width) | RSTN | 25 | 50 | μs | TA = 25℃, VCC = 15V, VCC_MODE = 0 | 81 | |
| VDD5 电压 (LDO output voltage) | VDD5 | 4.7 | 5 | 5.3 | V | VCC = 7V ~ 24V, VCC_MODE = 0, TA = -40℃ ~ 85℃ | 82 |
| VBB 电压 (VBB voltage) | VBB | 9 | 10 | 11 | V | VCC = 12V ~ 30V | 82 |
| VBB 启动时间 (VBB start-up time) | 1 | ms | 使能至稳定值 95%输出，1μF 电容 | 82 | |||
| ƟJA 芯片结温相对环境温度 (junction-to-ambient, 2S2P PCB) | ƟJA | 47 | ℃/W | JEDEC 标准，2S2P PCB | 83 | ||
| ƟJA 芯片结温相对环境温度 (junction-to-ambient, 1S0P PCB) | ƟJA | 74 | ℃/W | JEDEC 标准，1S0P PCB | 83 | ||
| ƟJC 芯片结温相对封装表面温度 (junction-to-case, 1S0P PCB) | ƟJC | 20 | ℃/W | JEDEC 标准，1S0P PCB | 83 |
CAD (KiCad official)
- Symbol:
FU6831N - Footprint:
Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm - 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
fu6831n-etched.step/fu6831n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);fu6831n.step/fu6831n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Fortior Tech datasheet (292 pp, sha256
d5a21e4e7fe9a48c, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).