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ADUM163N1BRZ-RL7

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Analog Devices Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232adum163n1brz-rl7factory-2.0.0extractor-text

Verified ADUM163N1BRZ-RL7

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ADUM163N1BRZ-RL7 · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C660500, digikey 505-ADUM163N1BRZ-RL7TR-ND, mouser 584-ADUM163N1BRZ-RL7
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-4gmp_r6t/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ adum163n1brz-rl7.kicad_sym✓ adum163n1brz-rl7.kicad_mod✓ adum163n1brz-rl7.step
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3D Model

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Symbol & Footprint

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Contents

README

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ADUM163N1BRZ-RL7

Analog Devices · Digital Isolators · SOIC-16

ADUM163N1BRZ-RL7 from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for isolator side 1, specified at 1.7 V to 5.5 V in the recommended operating conditions.
2 VIA input Logic Input A; when the side 1 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry.
3 VIB input Logic Input B; when the side 1 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry.
4 VIC input Logic Input C; when the side 1 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry.
5 VOD output Logic Output D; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered.
6 VOE output Logic Output E; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered.
7 VOF output Logic Output F; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered.
8 GND1 power_in Ground 1; ground reference for isolator side 1.
9 GND2 power_in Ground 2; ground reference for isolator side 2.
10 VIF input Logic Input F; when the side 2 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry.
11 VIE input Logic Input E; when the side 2 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry.
12 VID input Logic Input D; when the side 2 supply is unpowered, this input must be held low to avoid powering the device through its ESD protection circuitry.
13 VOC output Logic Output C; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered.
14 VOB output Logic Output B; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered.
15 VOA output Logic Output A; for the ADuM163N1 (fail-safe high) model, it is driven high when the input-side supply of its channel is unpowered.
16 VDD2 power_in Supply voltage for isolator side 2, specified at 1.7 V to 5.5 V in the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Temperature TA -40 125 °C 14
Supply Voltages VDD1, VDD2 1.7 5.5 V 14
Input Signal Rise and Fall Times 1 ms Printed as Rating 1.0 ms with no min/max qualifier 14
Storage Temperature Range TST -65 150 °C 15
Ambient Operating Temperature Range TA -40 125 °C 15
Supply Voltages VDD1, VDD2 -0.5 7 V 15
Input Voltages VIA, VIB, VIC, VID, VIE, VIF -0.5 V Maximum printed as VDDI1 + 0.5 V (not numeric) 15
Output Voltages VOA, VOB, VOC, VOD, VOE, VOF -0.5 V Maximum printed as VDDO2 + 0.5 V (not numeric) 15
Side 1 Average Output Current per Pin IO1 -10 10 mA Average output current per pin 15
Side 2 Average Output Current per Pin IO2 -10 10 mA Average output current per pin 15
Common-Mode Transients -150 150 kV/µs Across the insulation barrier 15
Pulse Width PW 6.6 ns Within pulse width distortion (PWD) limit; all voltages 4
Data Rate 150 Mbps Within PWD limit; all voltages 4
Common-Mode Transient Immunity /CMH/ /CMH/ 75 100 kV/µs VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V; all voltages 4
Common-Mode Transient Immunity /CML/ /CML/ 75 100 kV/µs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V; all voltages 4
Input Current per Channel II -10 0.01 10 µA 0 V ≤ VIx ≤ VDDx; all voltages 4
Propagation Delay tPHL, tPLH (5 V operation) tPHL, tPLH 4.8 7.2 13 ns 50% input to 50% output 4
Pulse Width Distortion (5 V operation) PWD 0.5 4.5 ns /tPLH − tPHL/ 4
Channel Matching Codirectional (5 V operation) tPSKCD 0.5 4 ns 4
Channel Matching Opposing Direction (5 V operation) tPSKOD 0.5 4.5 ns 4
Logic Low Output Voltage (5 V operation) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 4
Logic Low Output Voltage (5 V operation) VOL 0.2 0.4 V IOx = 4 mA, VIx = VIxL 4
Quiescent Supply Current Side 1 (5 V operation) IDD1 (Q) 3 4.26 mA VI5 = 0 (N0), 1 (N1) 4
Quiescent Supply Current Side 2 (5 V operation) IDD2 (Q) 2.8 3.92 mA VI5 = 0 (N0), 1 (N1) 4
Quiescent Supply Current Side 1 (5 V operation) IDD1 (Q) 11.8 18.9 mA VI5 = 1 (N0), 0 (N1) 4
Quiescent Supply Current Side 2 (5 V operation) IDD2 (Q) 14.6 23 mA VI5 = 1 (N0), 0 (N1) 5
Propagation Delay tPHL, tPLH (3.3 V operation) tPHL, tPLH 4.8 6.8 14 ns 50% input to 50% output 6
Pulse Width Distortion (3.3 V operation) PWD 0.7 4.5 ns /tPLH − tPHL/ 6
Channel Matching Codirectional (3.3 V operation) tPSKCD 0.7 4 ns 6
Channel Matching Opposing Direction (3.3 V operation) tPSKOD 0.7 4.5 ns 6
Logic Low Output Voltage (3.3 V operation) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 6
Logic Low Output Voltage (3.3 V operation) VOL 0.2 0.4 V IOx = 2 mA, VIx = VIxL 6
Quiescent Supply Current Side 1 (3.3 V operation) IDD1 (Q) 2.8 4.16 mA VI5 = 0 (N0), 1 (N1) 6
Quiescent Supply Current Side 2 (3.3 V operation) IDD2 (Q) 2.6 3.82 mA VI5 = 0 (N0), 1 (N1) 6
Quiescent Supply Current Side 1 (3.3 V operation) IDD1 (Q) 11.5 18.5 mA VI5 = 1 (N0), 0 (N1) 6
Quiescent Supply Current Side 2 (3.3 V operation) IDD2 (Q) 14.3 22.5 mA VI5 = 1 (N0), 0 (N1) 7
Propagation Delay tPHL, tPLH (2.5 V operation) tPHL, tPLH 5 7 14 ns 50% input to 50% output 8
Pulse Width Distortion (2.5 V operation) PWD 0.7 5 ns /tPLH − tPHL/ 8
Channel Matching Codirectional (2.5 V operation) tPSKCD 0.7 5 ns 8
Channel Matching Opposing Direction (2.5 V operation) tPSKOD 0.7 5 ns 8
Logic Low Output Voltage (2.5 V operation) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 8
Logic Low Output Voltage (2.5 V operation) VOL 0.2 0.4 V IOx = 2 mA, VIx = VIxL 8
Quiescent Supply Current Side 1 (2.5 V operation) IDD1 (Q) 2.7 4.08 mA VI5 = 0 (N0), 1 (N1) 8
Quiescent Supply Current Side 2 (2.5 V operation) IDD2 (Q) 2.55 3.72 mA VI5 = 0 (N0), 1 (N1) 8
Quiescent Supply Current Side 1 (2.5 V operation) IDD1 (Q) 11.5 18.4 mA VI5 = 1 (N0), 0 (N1) 8
Quiescent Supply Current Side 2 (2.5 V operation) IDD2 (Q) 14.3 22.3 mA VI5 = 1 (N0), 0 (N1) 9
Propagation Delay tPHL, tPLH (1.8 V operation) tPHL, tPLH 5.8 8.7 15 ns 50% input to 50% output 10
Pulse Width Distortion (1.8 V operation) PWD 0.7 5 ns /tPLH − tPHL/ 10
Channel Matching Codirectional (1.8 V operation) tPSKCD 0.7 5 ns 10
Channel Matching Opposing Direction (1.8 V operation) tPSKOD 0.7 5 ns 10
Logic Low Output Voltage (1.8 V operation) VOL 0 0.1 V IOx = 20 µA, VIx = VIxL 10
Logic Low Output Voltage (1.8 V operation) VOL 0.2 0.4 V IOx = 2 mA, VIx = VIxL 10
Quiescent Supply Current Side 1 (1.8 V operation) IDD1 (Q) 2.6 4.03 mA VI5 = 0 (N0), 1 (N1) 10
Quiescent Supply Current Side 2 (1.8 V operation) IDD2 (Q) 2.5 3.72 mA VI5 = 0 (N0), 1 (N1) 10
Quiescent Supply Current Side 1 (1.8 V operation) IDD1 (Q) 11.3 18.3 mA VI5 = 1 (N0), 0 (N1) 10
Quiescent Supply Current Side 2 (1.8 V operation) IDD2 (Q) 14 22 mA VI5 = 1 (N0), 0 (N1) 11
IC Junction to Ambient Thermal Resistance θJA 75 °C/W Thermocouple located at center of package underside 12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN EN IEC 60747 (VDE 0884-17) each ADuM160N/ADuM161N/ADuM162N/ADuM163N in the R-16, narrow-body (SOIC_N) package is proof tested by applying an insulation test voltage ≥ 1059 V pea 13

CAD (KiCad official)

  • Symbol: ADUM163N1BRZ-RL7
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: adum163n1brz-rl7-etched.step / adum163n1brz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum163n1brz-rl7.step / adum163n1brz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (25 pp, sha256 716242daccaa34f4, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF