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Contents

README

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ADS7950SBRGET

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-24-EP(4x4)

ADS7950SBRGET from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 +VA power_in Analog power supply, 2.7 V to 5.25 V recommended, with a 1-µF ceramic decoupling capacitor required at each supply pin.
2 AGND power_in Analog ground; all channel inputs share this common analog ground.
3 MXO output Multiplexer output, which may be shorted to AINP or routed through a buffer or signal-conditioning stage, with source impedance kept to 50 Ω or less when shorted directly.
4 AINP input ADC input signal, with AINP to AGND limited to -0.3 V to +VA + 0.3 V as an absolute maximum.
5 AINM input ADC input ground, the negative reference for the ADC input.
6 NC unconnected Internally not connected; do not float this pin and connect it to ground.
7 NC unconnected Internally not connected; do not float this pin and connect it to ground.
8 CH3 input Analog input channel 3 for the multiplexer, with CHn to AGND limited to -0.3 V to +VA + 0.3 V.
9 CH2 input Analog input channel 2 for the multiplexer, with CHn to AGND limited to -0.3 V to +VA + 0.3 V.
10 CH1 input Analog input channel 1 for the multiplexer, with CHn to AGND limited to -0.3 V to +VA + 0.3 V.
11 CH0 input Analog input channel 0 for the multiplexer, with CHn to AGND limited to -0.3 V to +VA + 0.3 V.
12 NC unconnected Internally not connected; do not float this pin and connect it to ground.
13 NC unconnected Internally not connected; do not float this pin and connect it to ground.
14 +VA power_in Analog power supply, 2.7 V to 5.25 V recommended, with a 1-µF ceramic decoupling capacitor required at each supply pin.
15 AGND power_in Analog ground; all channel inputs share this common analog ground.
16 CS input Active-low chip-select input; the input signal is sampled on its falling edge and a frame ends only after 16 SCLK clocks have elapsed.
17 SCLK input Serial clock input, up to 20 MHz, used for conversion, serial data output and serial data input.
18 SDI input Serial data input for the 16-bit control word, latched on each SCLK rising edge starting with the first clock.
19 SDO output Serial data output carrying the channel address and conversion result, which goes to the 3-state condition after the 16th SCLK falling edge.
20 BDGND power_in Digital ground for the digital I/O interface.
21 +VBD power_in Digital I/O supply, 1.7 V to +VA recommended, with a 1-µF ceramic decoupling capacitor required at the pin.
22 GPIO0 bidirectional General-purpose input or output; when configured it serves as an active-high high- or low-alarm output on the VQFN package.
23 REFM input Reference ground for the external 2.5 V reference, which needs a 10-µF ceramic decoupling capacitor to REFP placed next to the device.
24 REFP input External reference input, 2 V to 3 V recommended (2.5 V nominal, ±10 mV), requiring a 10-µF ceramic decoupling capacitor to REFM.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Data Acquisition
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Full-scale input span 0 V Range 1 12
Absolute input range -0.2 V Range 1 12
Integral linearity -1 0.5 1 LSB ADS795XSB 12
Differential linearity -0.99 0.5 1 LSB ADS795XSB 12
Offset error -3.5 1.1 3.5 LSB 12
Gain error -2 0.2 2 LSB Range 1 12
Gain error -0.2 0.2 LSB Range 2 12
Total unadjusted error (TUE) -2 2 LSB 12
Signal-to-noise ratio 70 71.7 dB 100 kHz, ADS795XSB 13
Signal-to-noise + distortion 69 71.3 dB 100 kHz, ADS795XSB 13
VREF reference voltage at REFP VREF 2 2.5 3 V 13
High threshold range 0 4092 LSB 13
Low threshold range 0 4092 LSB 13
Low-level input voltage VIL 0.8 V +VBD = 5 V 13
Low-level input voltage VIL 0.4 V +VBD = 3 V 13
Low-level output voltage VOL 0.4 V At Isink = 200 μA 13
+VA supply voltage 2.7 3.3 5.25 V 13
+VBD supply voltage 1.7 3.3 5.25 V 13
Supply current (normal mode), 1 MHz throughput 2.3 3 mA At +VA = 4.7 to 5.25 V 13
Supply current (normal mode), static state 1.1 1.5 mA At +VA = 4.7 to 5.25 V 13
Analog power-supply voltage V(+VA) 2.7 3.3 5.25 V 10
Digital I/O-supply voltage V(+VBD) 1.7 3.3 V 10
Reference voltage V(REF) 2 2.5 3 V 10
SCLK frequency ƒ(SCLK) 20 MHz 10
Operating temperature range TA -40 125 °C 10
AINP or CHn to AGND -0.3 V 10
+VA to AGND, +VBD to BDGND -0.3 7 V 10
Digital input voltage to BDGND -0.3 7 V 10
Digital output to BDGND -0.3 V 10
Input current to any pin except supply pins -10 10 mA 10
Operating temperature -40 125 °C 10
Junction temperature (TJ Max) 150 °C 10
Storage temperature (Tstg) -65 150 °C 10
Input capacitance 15 pF 12
Input leakage current 61 nA TA = 125°C 12
Resolution 12 Bits 12
No missing codes 12 Bits ADS795XSB 12
Conversion time 800 ns 20 MHz SCLK 12
Acquisition time 325 ns 12
Maximum throughput rate 1 MHz 20 MHz SCLK 12
Step response 150 ns 12
Total harmonic distortion -82 dB 100 kHz 13
Spurious free dynamic range 84 dB 100 kHz 13
Small signal bandwidth 47 MHz At -3 dB 13
Channel-to-channel crosstalk (isolation) -95 dB Any off-channel with 100 kHz, full-scale input to channel being sampled with DC input 13
Channel-to-channel crosstalk (memory) -85 dB From previously sampled to channel with 100 kHz, full-scale input to channel being sampled with DC input 13
Reference input resistance 100 kΩ At fsample = 1 MHz 13
Supply current (normal mode), 1 MHz throughput 1.8 mA At +VA = 2.7 to 3.6 V 13
Supply current (normal mode), static state 1.05 mA At +VA = 2.7 to 3.6 V 13
Power-down state supply current 1 μA 13
+VBD supply current 1 mA +VA = 5.25 V, fs = 1 MHz 13
Junction-to-ambient thermal resistance RθJA 36.9 °C/W RGE (VQFN) 24 pins 11
Junction-to-case (top) thermal resistance RθJC(top) 39.3 °C/W RGE (VQFN) 24 pins 11
Junction-to-board thermal resistance RθJB 14.7 °C/W RGE (VQFN) 24 pins 11
Junction-to-top characterization parameter ψJT 0.7 °C/W RGE (VQFN) 24 pins 11
Junction-to-board characterization parameter ψJB 14.8 °C/W RGE (VQFN) 24 pins 11
Junction-to-case (bottom) thermal resistance RθJC(bot) 5.6 °C/W RGE (VQFN) 24 pins 11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper • A copper fill area underneath the device ties the AGND, BDGND, AINM, and REFM pins together. This 52

CAD (KiCad official)

  • Symbol: ADS7950SBRGET
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ads7950sbrget-etched.step / ads7950sbrget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads7950sbrget.step / ads7950sbrget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (87 pp, sha256 e7922065e4d1691d, retrieved 2026-11-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF