component

AD5621BKSZ-500RL7

Public Made by Adom

by adom

Analog Devices Digital To Analog Converters (DAC), SC-70-6(SOT-363). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionad5621bksz-500rl7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

AD5621BKSZ-500RL7

Analog Devices · Digital To Analog Converters (DAC) · SC-70-6(SOT-363)

AD5621BKSZ-500RL7 from Analog Devices, in a SC-70-6(SOT-363). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC input Level-triggered active-low frame synchronization input; when SYNC goes low the input shift register is enabled, and if SYNC is taken high before the 16th clock edge its rising edge interrupts the write and the DAC ignores it.
2 SCLK input Serial clock input whose falling edge clocks data into the input shift register, with data transfer rates up to 30 MHz.
3 SDIN input Serial data input to a 16-bit shift register, with data clocked in on the falling edge of the serial clock.
4 VDD power_in Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled to GND.
5 GND power_in Ground reference point for all circuitry on the device.
6 VOUT output Analog buffered DAC output voltage from an output amplifier with rail-to-rail operation.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SC-70-6(SOT-363)
Category Data Acquisition
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD VDD 2.7 5.5 V All digital inputs at 0 V or VDD 4
Relative accuracy (INL), B grade INL -1 1 LSB Linearity calculated using reduced code range: Code 64 to Code 4032 3
Differential nonlinearity (DNL), B grade DNL -0.5 0.5 LSB Guaranteed monotonic by design 3
Zero-code error 0.5 10 mV All 0s loaded to DAC register 3
Full-scale error -0.5 0.5 mV All 1s loaded to DAC register 3
Offset error -10 0.063 10 mV 3
Gain error -0.037 0.0004 0.037 %FSR 3
Output voltage range VOUT 0 V Printed upper limit is VDD 3
Output voltage settling time 6 10 μs Code ¼ scale to ¾ scale 3
Capacitive load stability 470 pF RL = ∞ 3
Capacitive load stability 1000 pF RL = 2 kΩ 3
Input current -2 2 μA Total current flowing into all pins 3
Input high voltage VINH 1.8 V VDD = 4.7 V to 5.5 V 3
Input high voltage VINH 1.4 V VDD = 2.7 V to 3.6 V 3
Input low voltage VINL 0.8 V VDD = 4.7 V to 5.5 V 3
Input low voltage VINL 0.6 V VDD = 2.7 V to 3.6 V 3
IDD normal mode IDD 75 100 μA DAC active, excluding load current; VDD = ±4.5 V to ±5.5 V; VIH = VDD and VIL = GND 4
IDD normal mode IDD 60 90 μA DAC active, excluding load current; VDD = ±2.7 V to ±3.6 V; VIH = VDD and VIL = GND 4
IDD all power-down modes IDD 0.5 μA VDD = ±4.5 V to ±5.5 V; VIH = VDD and VIL = GND 4
IDD all power-down modes IDD 0.2 μA VDD = ±2.7 V to ±3.6 V; VIH = VDD and VIL = GND 4
Maximum SCLK frequency fSCLK 30 MHz 4
SCLK cycle time t1 33 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
SCLK high time t2 5 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
SCLK low time t3 5 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
SYNC to SCLK falling edge setup time t4 10 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
Data setup time t5 5 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
Data hold time t6 4.5 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
Minimum SYNC high time t8 20 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
SYNC rising edge to next SCLK falling edge ignored t9 13 ns VDD = 2.7 V to 5.5 V; tr = tf = 1 ns/V 4
VDD to GND VDD -0.3 7 V 5
Digital input voltage to GND VIN -0.3 V Printed upper limit is VDD + 0.3 V 5
VOUT to GND VOUT -0.3 V Printed upper limit is VDD + 0.3 V 5
Operating temperature range, industrial (A/B grades) TA -40 125 °C A/B grades 5
Storage temperature range TSTG -65 160 °C 5
Maximum junction temperature TJ 150 °C 5
Lead temperature, soldering, vapor phase 215 °C 60 sec 5
Lead temperature, soldering, infrared 220 °C 15 sec 5
Thermal impedance, junction-to-ambient (SC70) θJA 433.34 °C/W SC70 package 5
Thermal impedance, junction-to-case (SC70) θJC 149.47 °C/W SC70 package 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing Abs ESD (Human Body Model) 2.0 kV Stresses at or above those listed under Absolute Maximum 5

CAD (KiCad official)

  • Symbol: AD5621BKSZ-500RL7
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6(SOT-363) (KiCad packages3D, STEP)
  • 3D model files: ad5621bksz-500rl7-etched.step / ad5621bksz-500rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5621bksz-500rl7.step / ad5621bksz-500rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (21 pp, sha256 1f8185bd626f1e11, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF