component
HC32F334JAUI-ZFN48TR
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), QFN-48-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHC32F334JAUI-ZFN48TR
XHSC · Microcontrollers (MCU/MPU/SOC) · QFN-48-EP(5x5)
HC32F334JAUI-ZFN48TR from XHSC, in a QFN-48-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PF2 | bidirectional | 5 V-tolerant GPIO (input must not exceed 5 V, and internal pull-up/pull-down is disabled when the input exceeds VCC) also providing EIRQ2 interrupt input and EMB, USART, PLA and Timer4/Timer6/TimerA alternate functions. |
| 2 | PC13 | bidirectional | 5 V-tolerant GPIO (input must not exceed 5 V; pulls disabled above VCC) also providing EIRQ13 with WKUP3_1 wake-up input, RTC_OUT, PLA and Timer4/Timer6 alternate functions. |
| 3 | PC14/XTAL32_IN | input | External secondary (32 kHz) oscillator input, also usable as 5 V-tolerant GPIO PC14 with EIRQ14 and PLA/Timer4 alternate functions. |
| 4 | PC15/XTAL32_OUT | output | External secondary (32 kHz) oscillator output, also usable as 5 V-tolerant GPIO PC15 with EIRQ15 and Timer4 alternate functions. |
| 5 | PF0/XTAL_IN | input | External main oscillator (XTAL) interface input, also usable as 5 V-tolerant GPIO PF0 with EIRQ0, CMP3_OUT and Timer4/Timer6 alternate functions. |
| 6 | PF1/XTAL_OUT | output | External main oscillator (XTAL) interface output, also usable as 5 V-tolerant GPIO PF1 with EIRQ1, CMP1_OUT and Timer4 alternate functions. |
| 7 | NRST | input | Reset terminal, active low; if unused it should be connected to VCC through a pull-up resistor. |
| 8 | AVSS/VREFL | power_in | Analog ground and low analog reference; tie to VSS when the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply at the same voltage as VCC (1.8-3.63 V) and high analog reference; tie to VCC when the analog modules are not used, and analog input voltages must not exceed AVCC/VREFH. |
| 10 | PA0 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC1_IN0 with EIRQ0/WKUP0_0, CMP1_OUT, FCMREF and Timer6/TimerA alternate functions. |
| 11 | PA1 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC1_IN1, RTC_CLK1 input, EIRQ1, EMB, HRPWM and TimerA alternate functions. |
| 12 | PA2 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC1_IN2, CMP1_INM2, ADTRG1, EIRQ2, CMP1/CMP2_OUT, PLA0 and TimerA alternate functions. |
| 13 | PA3 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC1_IN3, CMP1/2/3 positive inputs, ADTRG2, EIRQ3, PLA4 and TimerA alternate functions. |
| 14 | PA4 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC12_IN4, DAC1_OUT1, CMP1/2/3 negative inputs, EIRQ4, USART1/2 clock, PLA5 and TimerA alternate functions. |
| 15 | PA5 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC12_IN5, DAC1_OUT2, EIRQ5, PLA6 and TimerA alternate functions. |
| 16 | PA6 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC123_IN6, DAC2_OUT1, EIRQ6, CMP1_OUT, EMB and TimerA alternate functions. |
| 17 | PA7 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC123_IN7, CMP1_INP1, ADTRG3, EIRQ7, CMP2_OUT, PLA1 and Timer6/TimerA alternate functions. |
| 18 | PB0 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC123_IN8, CMP2_INP1, ADTRG1, EIRQ0, RTC_OUT, PLA1 and Timer6/TimerA alternate functions. |
| 19 | PB1 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC123_IN9, ADTRG2, EIRQ1 with WKUP0_1, CMP1/2_OUT, HRPWM_SCOUT and MCO_1 alternate functions. |
| 20 | PB2 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC3_IN10, CMP2_INM2, ADTRG3, EIRQ2 with WKUP0_2, USART1/4 clock, HRPWM_TRIGA and MCO_2 alternate functions. |
| 21 | PB10 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC3_IN11, EIRQ10, HRPWM_EEV9, EMB and TimerA alternate functions. |
| 22 | PB11 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also CMP3_INP1, EIRQ11, HRPWM_EEV7, EMB and Timer6/TimerA alternate functions. |
| 23 | VSS | power_in | Ground, 0 V reference for VCC. |
| 24 | VCC | power_in | Power supply rated 1.8-3.63 V, decoupled close to VSS with ceramic capacitors as specified in the electrical characteristics. |
| 25 | PB12 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC3_IN0, EIRQ12, HRPWM_4_PWMA, EMB_PORT1_IN1, USART1/3 clock and PLA8 alternate functions. |
| 26 | PB13 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC3_IN1, EIRQ13, HRPWM_4_PWMB, PLA9 and Timer6/TimerA alternate functions. |
| 27 | PB14 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC3_IN2, EIRQ14, HRPWM_5_PWMA, PLA10, Timer4/Timer6 and TimerA alternate functions. |
| 28 | PB15 | bidirectional | 5 V-tolerant GPIO that, when used as analog input, must not exceed AVCC/VREFH; also ADC3_IN3, CMP3_INM2, RTC_CLK2, EIRQ15, CMP1_OUT and HRPWM_5_PWMB alternate functions. |
| 29 | PA8 | bidirectional | 5 V-tolerant GPIO also providing EXVREF external reference input, EIRQ8 with WKUP2_0, TRACED0, HRPWM_2_PWMA, USART1/2 clock, CTCREF and MCO_1 alternate functions. |
| 30 | PA9 | bidirectional | 5 V-tolerant GPIO also providing EIRQ9, TRACECLK, HRPWM_2_PWMB, EMB_PORT1_IN3, TimerA, MCO_2 and EMB alternate functions. |
| 31 | PA10 | bidirectional | 5 V-tolerant GPIO also providing EIRQ10 with WKUP2_2, TRACED1, HRPWM_3_PWMA, CMP3_OUT, EMB_PORT1_IN5, PLA2 and Timer4 alternate functions. |
| 32 | PA11 | bidirectional | 5 V-tolerant GPIO also providing EIRQ11 with WKUP2_3, TRACED2, HRPWM_3_PWMB, CMP1_OUT, EMB_PORT1_IN2, PLA3 and Timer6 alternate functions. |
| 33 | PA12 | bidirectional | 5 V-tolerant GPIO also providing EIRQ12 with WKUP3_0, TRACED3, CMP1/2_OUT, SPI_NSS1, HRPWM_EEV2, EMB and FCMREF alternate functions. |
| 34 | PA13 | bidirectional | 5 V-tolerant GPIO also providing the JTMS/SWDIO debug data pin, EIRQ13, EMB_PORT1_IN5, HRPWM_EEV3, USART4 clock, PLA8, CMP3_OUT and ADTRG3 alternate functions. |
| 35 | VSS | power_in | Ground, 0 V reference for VCC. |
| 36 | VCC | power_in | Power supply rated 1.8-3.63 V, decoupled close to VSS with ceramic capacitors as specified in the electrical characteristics. |
| 37 | PA14 | bidirectional | 5 V-tolerant GPIO also providing the JTCK/SWCLK debug clock pin, EIRQ14 with WKUP3_2, Timer4/Timer6 and ADTRG2 alternate functions. |
| 38 | PA15 | bidirectional | 5 V-tolerant GPIO also providing the JTDI debug input, EIRQ15 with WKUP3_3, HRPWM_EEV1, EMB_PORT1_IN2, PLA3 and TimerA alternate functions. |
| 39 | PB3 | bidirectional | 5 V-tolerant GPIO also providing the JTDO/TRACESWO debug output, EIRQ3 with WKUP0_3, HRPWM_EEV9, HRPWM_SCOUT, PLA0 and Timer4/Timer6/TimerA alternate functions. |
| 40 | PB4 | bidirectional | 5 V-tolerant GPIO also providing the NJTRST debug reset input, EIRQ4 with WKUP1_0, HRPWM_EEV7, PLA1, Timer4/Timer6, EMB and MCO_2 alternate functions. |
| 41 | PB5 | bidirectional | 5 V-tolerant GPIO also providing EIRQ5 with WKUP1_1, HRPWM_EEV6, USART1/2 clock, PLA2, Timer4/Timer6, EMB and MCO_1 alternate functions. |
| 42 | PB6 | bidirectional | 5 V-tolerant GPIO also providing EIRQ6 with WKUP1_2, SPI_NSS2, HRPWM_EEV4, HRPWM_TRIGB, CTCREF, CMP1_OUT, ADTRG1 and Timer4/Timer6 alternate functions. |
| 43 | PB7 | bidirectional | 5 V-tolerant GPIO also providing EIRQ7 with WKUP1_3, EMB_PORT1_IN1, HRPWM_EEV3, FCMREF, CMP2_OUT, ADTRG2 and TimerA/Timer6 alternate functions. |
| 44 | PF3/MD | input | Mode input that must be held low when NRST is released; a 4.7 kOhm pull-down to VSS is recommended. |
| 45 | PB8 | bidirectional | 5 V-tolerant GPIO also providing the PVD2 external comparison input PVD2EXINP, EIRQ8, SPI_NSS3, EMB_PORT1_IN3, HRPWM_EEV8, ADTRG1 and FCMREF alternate functions. |
| 46 | PB9 | bidirectional | 5 V-tolerant GPIO also providing EIRQ9 with WKUP2_1, CMP1/2_OUT, EMB_PORT1_IN4, HRPWM_EEV5, Timer4/Timer6/TimerA alternate functions. |
| 47 | VSS | power_in | Ground, 0 V reference for VCC. |
| 48 | VCC | power_in | Power supply rated 1.8-3.63 V, decoupled close to VSS with ceramic capacitors as specified in the electrical characteristics. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | QFN-48-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC 供电电压 (模拟、数字电源，1.8~3.63V) | VCC | 1.8 | 3.63 | V | 41 | ||
| 数据输出有效时间 tv(SO) 从机模式 | tv(SO) | 15 | ns | 从机模式，2.7V≤Vcc≤3.63V | 69 | ||
| 数据输出有效时间 tv(SO) 从机模式 | tv(SO) | 26 | ns | 从机模式，1.8V≤Vcc＜2.7V | 69 | ||
| 数据输入建立时间 tsu(SI) 从机模式 | tsu(SI) | 4 | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 | ||
| 数据输入保持时间 th(SI) 从机模式 | th(SI) | 3 | ns | 从机模式，1.8V≤Vcc≤3.63V | 69 | ||
| 数据输入建立时间 tsu(MI) 主机模式 | tsu(MI) | 5 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| 数据输入建立时间 tsu(MI) 主机模式 | tsu(MI) | 9 | ns | 主机模式，1.8V≤Vcc＜2.7V | 69 | ||
| 数据输入保持时间 th(MI) 主机模式 | th(MI) | 5 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| 数据输入保持时间 th(MI) 主机模式 | th(MI) | 15 | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 | ||
| 数据输出有效时间 tv(MO) 主机模式 | tv(MO) | 4 | ns | 主机模式，2.7V≤Vcc≤3.63V | 69 | ||
| 数据输出有效时间 tv(MO) 主机模式 | tv(MO) | 9 | ns | 主机模式，1.8V≤Vcc≤2.7V | 69 | ||
| SCL频率 | fSCL | 0 | 100 | KHz | 标准模式（SM） | 68 | |
| SCL频率 | fSCL | 0 | 400 | KHz | 快速模式（FM） | 68 | |
| SCL频率 | fSCL | 0 | 1000 | KHz | 快速模式Plus（FM+） | 68 | |
| 开始条件/重新开始条件Hold | tHD;STA | 4 | μs | 标准模式（SM） | 68 | ||
| 开始条件/重新开始条件Hold | tHD;STA | 0.6 | μs | 快速模式（FM） | 68 | ||
| 开始条件/重新开始条件Hold | tHD;STA | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| SCL低电平 | tLOW | 4.7 | μs | 标准模式（SM） | 68 | ||
| SCL低电平 | tLOW | 1.3 | μs | 快速模式（FM） | 68 | ||
| SCL低电平 | tLOW | 0.5 | μs | 快速模式Plus（FM+） | 68 | ||
| SCL高电平 | tHIGH | 4 | μs | 标准模式（SM） | 68 | ||
| SCL高电平 | tHIGH | 0.6 | μs | 快速模式（FM） | 68 | ||
| SCL高电平 | tHIGH | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| 重新开始条件Setup | tSU;STA | 4.7 | μs | 标准模式（SM） | 68 | ||
| 重新开始条件Setup | tSU;STA | 0.6 | μs | 快速模式（FM） | 68 | ||
| 重新开始条件Setup | tSU;STA | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| 数据Hold | tHD;DAT | 0 | μs | 标准模式（SM） | 68 | ||
| SCL/SDA的上升时间 | tR | 1000 | ns | 标准模式（SM） | 68 | ||
| SCL/SDA的上升时间 | tR | 300 | ns | 快速模式（FM） | 68 | ||
| SCL/SDA的上升时间 | tR | 120 | ns | 快速模式Plus（FM+） | 68 | ||
| SCL/SDA的下降时间 | tF | 300 | ns | 标准模式（SM） | 68 | ||
| SCL/SDA的下降时间 | tF | 120 | ns | 快速模式Plus（FM+） | 68 | ||
| 停止条件Setup | tSU;STO | 4 | μs | 标准模式（SM） | 68 | ||
| 停止条件Setup | tSU;STO | 0.6 | μs | 快速模式（FM） | 68 | ||
| 停止条件Setup | tSU;STO | 0.26 | μs | 快速模式Plus（FM+） | 68 | ||
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 4.7 | μs | 标准模式（SM） | 68 | ||
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 1.3 | μs | 快速模式（FM） | 68 | ||
| 停止条件到开始条件间的BUS空闲时间 | tBUF | 0.5 | μs | 快速模式Plus（FM+） | 68 | ||
| 负载电容 | Cb | 400 | pF | 标准模式（SM） | 68 | ||
| 负载电容 | Cb | 550 | pF | 快速模式Plus（FM+） | 68 | ||
| 数字外部事件响应时间 | TLAT(DEEV) | 60 | 70 | ns | HRPWMEEVy输入到HRPWM__PWMA/B输出端口，30pF负载（同步模式） | 67 | |
| 最小外部事件脉冲宽度 | TW(EEV) | 12.5 | ns | 67 | |||
| 模拟外部事件响应时间 | TLAT(AEEV) | 75 | 85 | ns | CMPy_INPz输入到HRPWM__PWMA/B输出端口，30pF负载（同步模式） | 67 | |
| 外部事件反应jitter | TJIT (EEV) | 1 | tPCLK0 | HRPWM_EEVy输入到HRPWM__PWMA/B输出端口 | 67 | ||
| 同步输入信号最小脉宽 HRPWM_TRGA~D | Tw(TRGA-D) | 2 | tPCLK0 | 67 | |||
| 同步请求响应时间 | TRES(TRGA-D) | 4 | tPCLK0 | 67 | |||
| 同步输出信号最小脉宽 HRPWM_SYNCOUT | Tw(SYNCOUT) | 16 | 65535 | tPCLK0 | 67 |
CAD (KiCad official)
- Symbol:
HC32F334JAUI-ZFN48TR - Footprint:
Package_DFN_QFN:QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm - 3D model: QFN-48-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
hc32f334jaui-zfn48tr-etched.step/hc32f334jaui-zfn48tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f334jaui-zfn48tr.step/hc32f334jaui-zfn48tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (102 pp, sha256
bf3aa4841b430601, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).