component
ALTAIR05T-800
Public Made by Adomby adom
STMicroelectronics AC-DC Controllers And Regulators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownALTAIR05T-800
STMicroelectronics · AC-DC Controllers And Regulators · SOIC-16
ALTAIR05T-800 from STMicroelectronics, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SOURCE | passive | Power section source and PWM comparator input; MOSFET current is sensed via a resistor to GND and compared with an internal 0.75 V max reference, with 250 ns blanking, and a 1 V second level stops the IC until Vcc drops below 5 V. |
| 2 | SOURCE | passive | Power section source and PWM comparator input; MOSFET current is sensed via a resistor to GND and compared with an internal 0.75 V max reference, with 250 ns blanking, and a 1 V second level stops the IC until Vcc drops below 5 V. |
| 3 | Vcc | power_in | Supply voltage of the device, charged by the internal high-voltage start-up generator via an electrolytic capacitor to GND, with an optional 0.1 µF typ. bypass capacitor for a clean bias. |
| 4 | GND | power_in | Ground and current return for the signal part of the IC and the gate drive, kept separate from any pulsed current return. |
| 5 | IREF | passive | CC regulation loop reference voltage pin that needs an external capacitor to GND, used as the reference for the MOSFET peak drain current during CC regulation. |
| 6 | ZCD/FB | bidirectional | Transformer demagnetization sensing for quasi-resonant operation and output voltage monitor (error amplifier reference 2.5 V), with sunk/sourced current not to exceed ±2 mA (AMR) and no capacitor allowed to the auxiliary winding. |
| 7 | COMP | output | Output of the internal transconductance error amplifier, where the compensation network to GND is placed for voltage loop stability. |
| 8 | CDC | output | Cable drop compensation input that can sink current and provides a voltage below the 2.5 V internal reference proportional to DC load current via a resistor to ZCD/FB, left open if unused. |
| 9 | N.A. | unconnected | Not available; this pin must be left not connected. |
| 10 | N.A. | unconnected | Not available; this pin must be left not connected. |
| 11 | N.A. | unconnected | Not available; this pin must be left not connected. |
| 12 | N.C. | unconnected | Not internally connected; provision for clearance on the PCB to meet safety requirements. |
| 13 | DRAIN | passive | Drain of the internal 800 V power section, also sinking the high-voltage start-up generator current, connected to the internal metal frame for heat dissipation. |
| 14 | DRAIN | passive | Drain of the internal 800 V power section, also sinking the high-voltage start-up generator current, connected to the internal metal frame for heat dissipation. |
| 15 | DRAIN | passive | Drain of the internal 800 V power section, also sinking the high-voltage start-up generator current, connected to the internal metal frame for heat dissipation. |
| 16 | DRAIN | passive | Drain of the internal 800 V power section, also sinking the high-voltage start-up generator current, connected to the internal metal frame for heat dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source breakdown voltage | V(BR)DSS | 800 | V | ID < 100 µA; Tj = 25 °C | 7 | ||
| Off-state drain current | IDSS | 80 | µA | VDS = 750 V; Tj = 125 °C | 7 | ||
| Drain-source ON-state resistance | RDS(on) | 11 | 14 | Ω | Id = 100 mA; Tj = 25 °C | 7 | |
| Drain-source ON-state resistance | RDS(on) | 22 | 28 | Ω | Id = 100 mA; Tj = 125 °C | 7 | |
| Min. drain start voltage | VStart | 40 | 50 | 60 | V | Icharge < 100 µA | 7 |
| Vcc startup charge current | Icharge | 4 | 5.5 | 7 | mA | VDRAIN > VStart; VCC < VCCOn; Tj = 25 °C | 7 |
| Vcc restart voltage (Vcc falling) | VCCrestart | 9.5 | 10.5 | 11.5 | V | Parameters tracking each other | 7 |
| Vcc restart voltage after protection tripping | VCCrestart | 5 | V | After protection tripping | 7 | ||
| Operating range | Vcc | 11.5 | 23 | V | After turn-on | 7 | |
| Turn-on threshold | VccOn | 12 | 13 | 14 | V | Parameters tracking each other | 7 |
| Turn-off threshold | VccOff | 9 | 10 | 11 | V | Parameters tracking each other | 7 |
| Zener voltage | VZ | 23 | 25 | 27 | V | Icc = 20 mA | 7 |
| Start-up current | Iccstart-up | 200 | 300 | µA | See Figure 5 | 7 | |
| Quiescent current | Iq | 1 | 1.4 | mA | See Figure 6 | 7 | |
| Operating supply current @ 50 kHz | Icc | 1.4 | 1.7 | mA | See Figure 7 | 7 | |
| Fault quiescent current | Iq(fault) | 250 | 350 | µA | During hiccup and brownout | 7 | |
| Start timer period | TSTART | 100 | 125 | 175 | µs | 7 | |
| Restart timer period during burst mode | TRESTART | 400 | 500 | 700 | µs | 7 | |
| ZCD input bias current | IZCDb | 0.1 | 1 | µA | VZCD = 0.1 to 3 V | 7 | |
| ZCD upper clamp voltage | VZCDH | 3 | 3.3 | 3.6 | V | IZCD = 1 mA | 7 |
| ZCD lower clamp voltage | VZCDL | -90 | -60 | -30 | mV | IZCD = - 1 mA | 7 |
| ZCD arming voltage | VZCDA | 100 | 110 | 120 | mV | Positive-going edge | 8 |
| ZCD triggering voltage | VZCDT | 50 | 60 | 70 | mV | Negative-going edge | 8 |
| Min. source current during MOSFET ON-time | IZCDON | -25 | -50 | -75 | µA | 8 | |
| Trigger blanking time after MOSFET turn-off | TBLANK | 6 | µs | VCOMP ≥ 1.3 V | 8 | ||
| Trigger blanking time after MOSFET turn-off | TBLANK | 30 | µs | VCOMP = 0.9 V | 8 | ||
| Equivalent feedforward resistor | RFF | 45 | Ω | IZCD = 1mA | 8 | ||
| Voltage reference | VREF | 2.46 | 2.5 | 2.54 | V | Tj = 25°C; parameters tracking each other | 8 |
| Voltage reference | VREF | 2.42 | 2.58 | V | Tj = -40 to 125°C and Vcc = 12 V to 23 V | 8 | |
| Transconductance | gm | 1.3 | 2.2 | 3.2 | mS | ∆ICOMP = ±10 µA VCOMP = 1.65 V | 8 |
| Voltage gain | Gv | 73 | dB | Open loop | 8 | ||
| Gain-bandwidth product | GB | 500 | KHz | 8 | |||
| COMP source current | ICOMP | 70 | µA | VZCD = 2.3 V, VCOMP = 1.65 V | 8 | ||
| COMP sink current | ICOMP | 400 | µA | VZCD = 2.7 V, VCOMP = 1.65 V | 8 | ||
| Upper COMP voltage | VCOMPH | 2.7 | V | VZCD = 2.3 V | 8 | ||
| Lower COMP voltage | VCOMPL | 0.7 | V | VZCD = 2.7 V | 8 | ||
| Burst-mode threshold | VCOMPBM | 1 | V | 8 | |||
| Burst-mode hysteresis | Hys | 65 | mV | 8 | |||
| CDC voltage reference | VCDC | 2.4 | 2.5 | 2.6 | V | VCOMP = 1.1 V, ICDC = 1 µA | 8 |
| Maximum value of IREF voltage | VIREFx | 1.5 | 1.6 | 1.7 | V | VCOMP = VCOMPL | 8 |
| Current reference voltage | VCREF | 0.192 | 0.2 | 0.208 | V | 8 | |
| Leading-edge blanking | tLEB | 200 | 250 | 300 | ns | 8 | |
| Delay-to-output | td(H-L) | 300 | ns | 8 | |||
| Max. clamp value | VCSx | 0.7 | 0.75 | 0.8 | V | dVcs/dt = 200 mV/µs | 8 |
| Hiccup-mode OCP level | VCSdis | 0.92 | 1 | 1.08 | V | 8 | |
| Drain-to-source voltage | VDS | -1 | 800 | V | Pins 1,2,13-16 | 6 | |
| Drain current | ID | 1 | A | Pins 1,2,13-16 | 6 | ||
| Single pulse avalanche energy | Eav | 50 | mJ | Tj = 25 °C, ID = 1 A | 6 | ||
| Zero-current detector current | IZCD/FB | -2 | 2 | mA | Pin 6 | 6 | |
| Analog inputs and outputs | -0.3 | 3.6 | V | Pins 7, 8 | 6 | ||
| Maximum sunk current | ICDC | 200 | µA | Pin 8 | 6 | ||
| Power dissipation | Ptot | 0.9 | W | TA = 50 °C | 6 | ||
| Junction temperature range | Tj | -40 | 150 | °C | 6 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 6 | ||
| Thermal resistance, junction-to-pin | Rth j-pin | 10 | °C/W | 6 | |||
| Thermal resistance, junction-to-ambient | Rth j-amb | 110 | °C/W | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | Figure 2: Pin connection (top view) The copper area for heat dissipation has to be designed under the drain pins | 4 |
CAD (KiCad official)
- Symbol:
ALTAIR05T-800 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
altair05t-800-etched.step/altair05t-800-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);altair05t-800.step/altair05t-800.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (27 pp, sha256
ae03774cada5f6b7, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).