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TPS7A4301DGQR
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Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS7A4301DGQR
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · MSOP-10
TPS7A4301DGQR from Texas Instruments, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Output pin that needs a capacitor to ground for stability, with COUT of 1 μF to 100 μF (2.2 μF nominal recommended) placed close to the OUT and GND pins. |
| 2 | FB | input | Feedback input to the control-loop error amplifier that sets the OUT voltage through external resistors (adjustable version only) and must not be left floating. |
| 3 | PG | output | Open-drain power-good output that indicates when the output reaches VIT(PG, RISING); a pullup resistor must limit sink current, VPG is rated up to 18 V, and the pin may be left floating if unused. |
| 4 | MVSEL1 | input | MID_OUT voltage-select input that works with MVSEL2 to set VMID_OUT (10 V, 12 V, or 15 V); it must not float and should be tied to GND if not used, with a recommended maximum of 18 V. |
| 5 | GND | power_in | Ground pin for the device, which should be connected to a large-area GND plane for thermal performance. |
| 6 | EN | input | Precision enable pin that enables the device above VEN(HI) and disables it below VEN(LOW), can be left floating due to an internal pullup, and must not exceed 18 V if tied to IN. |
| 7 | MVSEL2 | input | MID_OUT voltage-select input that works with MVSEL1 to set VMID_OUT (10 V, 12 V, or 15 V); it must not float and should be tied to GND if not used, with a recommended maximum of 18 V. |
| 8 | MID_OUT | output | MID output pin that requires a capacitor to ground for stability, with CMID_OUT at least 3 × COUT to maintain stability and VMID_OUT of 10 V to 15 V. |
| 9 | NC | unconnected | No internal connection; this pin must be left floating to observe the high-voltage clearance between the IN and MID_OUT pins. |
| 10 | IN | input | Input pin with a supply range of 4 V to 85 V that requires a ceramic capacitor of at least 0.1 μF to ground placed as close to the IN and GND pins as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-10 |
| Category | Power Management (PMIC) |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
TPS7A4301DGQR - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
tps7a4301dgqr-etched.step/tps7a4301dgqr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a4301dgqr.step/tps7a4301dgqr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
6ab8280bee821dc9, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).